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PDF MAX1428 Data sheet ( Hoja de datos )
| Número de pieza | MAX1428 | |
| Descripción | 15-Bit 80Msps ADC | |
| Fabricantes | Maxim Integrated Products | |
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19-3433; Rev 0; 10/04
EVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
15-Bit, 80Msps ADC with -78.4dBFS
Noise Floor for IF Applications
General Description
The MAX1428 is a 5V, high-speed, high-performance
analog-to-digital converter (ADC) featuring a fully differ-
ential wideband track-and-hold (T/H) and a 15-bit con-
verter core. The MAX1428 is optimized for multichannel,
multimode receivers, which require the ADC to meet very
stringent dynamic performance requirements. With a
noise floor of -78.4dBFS, the MAX1428 allows for the
design of receivers with superior sensitivity.
The MAX1428 achieves two-tone, spurious-free dynamic
range (SFDR) of -82dBc for input tones of 69MHz and
71MHz. Its excellent signal-to-noise ratio (SNR) of 73.9dB
and single-tone SFDR performance (SFDR1/SFDR2) of
83dBc/91dBc at fIN = 70MHz and a sampling rate of
80Msps make this part ideal for high-performance digital
receivers.
The MAX1428 operates from an analog 5V and a digital
3V supply, features a 2.56VP-P full-scale input range,
and allows for a sampling speed of up to 80Msps. The
input T/H operates with a -1dB full-power bandwidth of
260MHz.
The MAX1428 features parallel, CMOS-compatible out-
puts in two’s-complement format. To enable the interface
with a wide range of logic devices, this ADC provides a
separate output driver power-supply range of 2.3V to
3.5V. The MAX1428 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Note that IF parts MAX1418, MAX1428, and MAX1430
(see Pin-Compatible Higher/Lower Speed Versions
Selection table) are recommended for applications that
require high dynamic performance for input frequen-
cies greater than fCLK/3. Unlike its baseband counter-
part MAX1427, the MAX1428 is optimized for input
frequencies greater than fCLK/3.
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Single- and Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
Power Amplifier Linearity Correction
Antenna Array Processing
Features
♦ 80Msps Minimum Sampling Rate
♦ -78.4dBFS Noise Floor
♦ Excellent Dynamic Performance
73.9dB SNR at fIN = 70MHz and AIN = -2dBFS
83dBc/91dBc Single-Tone SFDR1/SFDR2 at
fIN = 70MHz and AIN = -2dBFS
-82dB Multitone SFDR at fIN1 = 69MHz
and fIN2 = 71MHz
♦ Less than 0.25ps Sampling Jitter
♦ Fully Differential Analog Input Voltage Range of
2.56VP-P
♦ CMOS-Compatible Two’s-Complement Data Output
♦ Separate Data Valid Clock and Overrange Outputs
♦ Flexible-Input Clock Buffer
♦ EV Kit Available for MAX1428
(Order MAX1427EVKIT)
Ordering Information
PART
TEMP RANGE
MAX1428ETN
-40°C to +85°C
*EP = Exposed paddle.
PIN-PACKAGE
56 Thin QFN-EP*
Pin-Compatible Higher/Lower
Speed Versions Selection
PART
MAX1418
MAX1419
MAX1427
MAX1428
MAX1429
MAX1430
SPEED GRADE
(Msps)
65
65
80
80
100
100
TARGET
APPLICATION
IF
Baseband
Baseband
IF
Baseband
IF
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
15-Bit, 80Msps ADC with -78.4dBFS
Noise Floor for IF Applications
Typical Operating Characteristics
(AVCC = 5V, DVCC = DRVCC = 2.5V, INP and INN driven differentially with a -2dBFS amplitude, CLKP and CLKN driven differentially
with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 80MHz, TA = 25°C. All AC data is based on a 32k-point FFT
record and under coherent sampling conditions.)
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
0
fCLK = 80.0195MHz
-20
fIN = 15.0012MHz
AIN = -2.07dBFS
SNR = 75.4dBc
-40 SINAD = 75.1dBc
SFDR1 = 89.4dBc
SFDR2 = 99dBc
-60 HD2 = -92.1dBFS
HD3 = -91.4dBFS
-80
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
0
fCLK = 80.0195MHz
-20
fIN = 35.001186MHz
AIN = -2.07dBFS
SNR = 75dBc
-40 SINAD = 74.5dBc
SFDR1 = 86.2dBc
SFDR2 = 94.6dBc
-60 HD2 = -91.8dBFS
HD3 = -88.3dBFS
-80
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
0
fCLK = 80.0195MHz
-20
fIN = 69.9999MHz
AIN = -1.98dBFS
SNR = 73.9dBc
-40 SINAD = 73.2dBc
SFDR1 = 82.8dBc
SFDR2 = 95.3dBc
-60 HD2 = -90.3dBFS
HD3 = -84.7dBFS
-80
-100 -100
-100
-120
0
5 10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
-120
0
5 10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
-120
0
5 10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
0
fCLK = 80.019456MHz
-20
fIN = 168.09995MHz
AIN = -5.96dBFS
SNR = 69dBc
-40 SINAD = 67.8dBc
SFDR1 = 77.8dBc
SFDR2 = 79.8dBc
-60 HD2 = -85.6dBFS
HD3 = -83.8dBFS
-80
-100
-120
0
5 10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
0
fIN1 fCLK = 80.0195MHz
-20
fIN2 fIN1 = 68.9987MHz
AIN1 = -8.05dBFS
fIN2 = 71.0012MHz
-40 AIN2 = -8.06dBFS
IMD = -82dBc
-60
2fIN1 + fIN2 fIN1 + 2fIN2
-80 2fIN1 - fIN2
-100
-120
0
5 10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
SNR vs. ANALOG INPUT FREQUENCY
(fCLK = 80.0195MHz, AIN = -2dBFS)
77
76
75
74
73
72
71
70
69
68
5
25 45 65 85 105 125 145 165 185
fIN (MHz)
_______________________________________________________________________________________ 5
5 Page 
www.DataSheet4U.com
15-Bit, 80Msps ADC with -78.4dBFS
Noise Floor for IF Applications
• tSETUP: Time from data guaranteed valid until the ris-
ing edge of DAV
• tHOLD: Time from the rising edge of DAV until data is
no longer valid
• tCLKP: Time from the 50% point of the rising edge to
the 50% point of the falling edge of the clock signal
• tCLKN: Time from the 50% point of the falling edge to
the 50% point of the rising edge of the clock signal
The MAX1428 samples the input signal on the rising
edge of the input clock. Output data is valid on the ris-
ing edge of the DAV signal, with a data latency of three
clock cycles. Note that the clock duty cycle must be
50% ±5% for proper operation.
Digital Outputs (D0–D14, DAV, DOR)
The logic-high level of the CMOS-compatible digital
outputs (D0–D14, DAV, and DOR) can be set in the
2.3V to 3.5V range. This is accomplished by setting the
voltage at the DVCC and DRVCC pins to the desired
logic-high level. Note that the DVCC and DRVCC volt-
ages must be the same value.
For best performance, the capacitive loading on the digital
outputs of the MAX1428 should be kept as low as possible
(<10pF). Large capacitive loads result in large charging
currents during data transitions, which may feed back into
the analog section of the ADC and create distortion terms.
The loading capacitance is kept low by keeping the output
traces short and by driving a single CMOS buffer or latch
input (as opposed to multiple CMOS inputs).
Inserting small series resistors (220Ω or less) between
the MAX1428 outputs and the digital load, placed as
closely as possible to the output pins, is helpful in con-
trolling the size of the charging currents during data
transitions and can improve dynamic performance.
Keep the trace length from the resistor to the load as
short as possible to minimize trace capacitance.
The output data is in two’s complement format, as illus-
trated in Table 1.
Data is valid at the rising edge of DAV (Figure 4), and
DAV can be used as a clock signal to latch the output
data. The DAV output provides twice the drive strength
of the data outputs, and may therefore be used to drive
multiple data latches.
The DOR output is used to identify an overrange condi-
tion. If the input signal exceeds the positive or negative
full-scale range for the MAX1428, then DOR is asserted
high. The timing for DOR is identical to the timing for
the data outputs, and DOR therefore provides an over-
range indication on a sample-by-sample basis.
Table 1. MAX1428 Digital Output Coding
INP
ANALOG VOLTAGE LEVEL
INN
ANALOG VOLTAGE LEVEL
VREF + 0.64V
VREF - 0.64V
VREF
VREF
VREF - 0.64V
VREF + 0.64V
D14–D0
TWO’S COMPLEMENT CODE
011111111111111
(positive full scale)
000000000000000
(midscale + δ)
111111111111111
(midscale - δ)
100000000000000
(negative full scale)
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MAX1428.PDF ] | |
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