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PDF LC74793 Data sheet ( Hoja de datos )
| Número de pieza | LC74793 | |
| Descripción | VPS / PDC Slicer IC | |
| Fabricantes | Sanyo Semicon Device | |
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Ordering number : EN*5966
CMOS IC
LC74793, 74793JM
VPS / PDC Slicer IC
Preliminary
Overview
The LC74793/JM is a CMOS IC that provides PDS, VPS,
and UDT data acquisition functions. The LC74793/JM
supports microprocessor control of its operating modes
and microprocessor read out of data acquired in any of its
operating modes.
Features
• VPS data acquisition (5 or 11 to 15 bytes)
VPS: Video Program System
• PDC (8/30/2) data acquisition (13 to 25 bytes)
PDC: Program Delivery Control
• UDT (8/30/1) data acquisition (13 to 25 bytes)
UDT: Unified Date and Time
• Header (X/00) data acquisition (14 to 45 bytes)
• Status display (8/30/1, 8/30/2) data acquisition (26 to
45 bytes)
• Automatic VPS/PDC discrimination mode
• Built-in AFC and sync separator circuits
• Synchronization discrimination circuit
• I2C bus support
Package Dimensions
unit: mm
3067-DIP24S
[LC74793]
unit: mm
3112-MFP24S
[LC74793JM]
SANYO: DIP24S
SANYO: MFP24S
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D1898RM (OT) No. 5966-1/24
1 page  
LC74793, 74793JM
Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified.
Parameter
Output off leakage current
High-level output voltage
Low-level output voltage
Input current
Operating current drain
Symbol
Applicable pins
Conditions
Ileak2
VOH1
VOL1
VOL2
IIH
IIL
IDD1
SDA and DAV
SEPOUT, CPOUT, SYNCJDG,
HOUT, and VOUT
SEPOUT, CPOUT, SYNCJDG,
DAV, HOUT, and VOUT
SDA
RST, SDA, SCL, CTRL1, CTRL2,
VCOIN
VDD1 = 4.5 V,
IOH = –1.0 mA
VDD1 = 4.5 V
IOL = 1.0 mA
VDD1 = 5.0 V
IOL = 3.0 mA
VIN = VDD1
SDA, SCL, CTRL1, CTRL2,
VCOIN
VIN = VSS1
VDD1 and VDD2
With all outputs open
and a 17.734 MHz
crystal
Ratings
min typ
3.5
–1
max
1
Unit
µA
V
1.0 V
0.4 V
1 µA
µA
40 mA
Timing Characteristics
PDC and VPS Read and Write (I2C bus timing) at Ta = –30 to +70°C, VDD1 = 5±0.5 V
Parameter
SCL frequency
Bus release time
Start hold time
SCL low-level period
SCL high-level period
Data hold time
Data setup time
Rise time
Fall time
Stop setup time
Symbol
fSCL
tBUF
tHD; STA
tLOW
tHIGN
tHD; DAT
tSU; DAT
tR
tF
tSU; STO
Conditions
Ratings
min typ
4.7
4.0
4.7
4.0
0
250
4.0
max
100
1000
300
Unit
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
Supplementary Documentation
• PDC and VPS serial timing (I2C bus timing)
S: Start condition
P: Stop condition
No. 5966-5/24
5 Page 
LC74793, 74793JM
Command 3 (Synchronizing signal detection command 1)
• First byte
DA 0 to 7
7
6
5
4
3
2
1
0
Register
—
—
—
—
—
—
—
—
Status
1
1
1
1
0
0
1
1
Contents
Function
First byte identification bit
Command 3 identification code.
Synchronizing signal detection settings 1.
Notes
• Second byte
DA 0 to 7
7
6
Register
—
RN2
5 RN1
4 RN0
3 SN3
2 SN2
1 SN1
0 SN0
Status
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Contents
Function
Second byte identification bit
RN2
0
0
0
1
RN1
0
0
1
0
RN0
0
1
0
0
Number of HSYNC detections
0 (32)
4 (64)
8 (128)
16 (256)
SN3
0
0
0
0
1
SN2
0
0
0
1
0
SN1
0
0
1
0
0
SNO
0
1
0
0
0
Number of HSYNC detections
No detection performed
32
64
128
256
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
Notes
External synchronizing signal detection
control.
Signal absent → present discrimination.
Sets the sampling period during which SYNC
is continuously detected in the horizontal
synchronizing signal period (1H).
Values in parentheses apply when RNE0
(COM4) is set to 1.
External synchronizing signal
detection control.
Signal present → absent
discrimination.
Sets the sampling period during which
SYNC cannot be detected
consecutively in the horizontal
synchronizing signal period (1H).
No. 5966-11/24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LC74793.PDF ] | |
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