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PDF LC74792 Data sheet ( Hoja de datos )

Número de pieza LC74792
Descripción VPS / PDC Slicer IC
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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No Preview Available ! LC74792 Hoja de datos, Descripción, Manual

Ordering number : EN*5965
CMOS IC
LC74792, 74792JM
VPS / PDC Slicer IC
Preliminary
Overview
The LC74792/JM is a CMOS IC that provides PDC, VPS,
and UDT data acquisition functions. The LC74792/JM
supports microprocessor control of its operating modes
and microprocessor read out of data acquired in any of its
operating modes.
Features
• VPS data acquisition (5 or 11 to 15 bytes)
VPS: Video Program System
• PDC (8/30/2) data acquisition (13 to 25 bytes)
PDC: Program Delivery Control
• UDT (8/30/1) data acquisition (13 to 25 bytes)
UDT: Unified Date and Time
• Header (X/00) data acquisition (14 to 45 bytes)
• Status display (8/30/1, 8/30/2) data acquisition (26 to
45 bytes)
• Automatic VPS/PDC discrimination mode
• Built-in AFC and sync separator circuits
• Synchronization discrimination circuit
Package Dimensions
unit: mm
3067-DIP24S
[LC74792]
24 13
1 12
21.2
0.81 1.78 0.48
0.95
unit: mm
3112-MFP24S
24
[LC74792JM]
13
SANYO: DIP24S
1 12
12.6 0.15
0.35 1.0 0.8
SANYO: MFP24S
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
40299RM (OT) No. 5965-1/25

1 page




LC74792 pdf
LC74792, 74792JM
Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified.
Parameter
Output off leakage current
High-level output voltage
Low-level output voltage
Input current
Operating current drain
Symbol
Applicable pins
Conditions
Ileak2
VOH1
VOL1
VOL2
IIH
IIL
IDD1
DAV and SIO
SEPOUT, CPOUT, SYNCJDG,
HOUT, and VOUT
VDD1 = 4.5 V,
IOH = –1.0 mA
SEPOUT, CPOUT, SYNCJDG,
DAV, HOUT, and VOUT
VDD1 = 4.5 V
IOL = 1.0 mA
SIO
VDD1 = 5.0 V
IOL = 3.0 mA
RST, SIO, SCLK, CTRL1, CTRL2,
VCOIN
VIN = VDD1
SIO, SCLK, CTRL1, CTRL2,
VCOIN
VIN = VSS1
VDD1 and VDD2
With all outputs open
and a 17.734 MHz
crystal
Ratings
min typ
3.5
–1
max
1
Unit
µA
V
1.0 V
0.4 V
1 µA
µA
40 mA
Timing Characteristics
[Write] (Refer to Figure 1) at Ta = –30 to +70°C, VDD1 = 5±0.5 V
Parameter
Minimum input pulse width
Data setup time
Data setup time
1-word write time
Symbol
tw (sclk)
tw (cs)
tsu (cs)
tsu (sin)
th (cs)
th (sin)
tword
twt
Conditions
SCLK
CS pin (while CS = "H")
CS
SIN
CS
SIN
8-bit data write time
RAM data write time
min
200
1
200
200
2
200
4.2
1
Ratings
typ
max
[Read] (Refer to Figure 2) (in case of N-ch open-drain type) at Ta = –30 to +70°C, VDD1 = 5±0.5 V
Parameter
Symbol
Minimum input pulse width
Data setup time
Output delay time
tCKCY
tCKL
tCKH
tICK
tCKO
SCLK
SCLK
SCLK
SCLK
SIO
Note: In case of CMOS output type, depends on OSD timing.
Conditions
min
2
1
1
10
Ratings
typ
max
0.5
Unit
ns
µs
ns
ns
µs
ns
µs
µs
Unit
µs
µs
µs
µs
µs
No. 5965-5/25

5 Page





LC74792 arduino
LC74792, 74792JM
Command 2 (VPS/PDC control command 2)
• First byte
DA 0 to 7
7
6
5
4
3
2
1
0
Register
Status
1
1
1
1
0
0
1
0
Contents
Function
First byte identification bit
Command 2 identification code.
VPS/PDC control settings 2.
Notes
• Second byte
DA 0 to 7
7
6
Register
VMWSE2
5 VMWSEL
4 HBS2
3 HBS1
2 BMS
1 EMS
0 DCE
Status
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Contents
Function
Second byte identification bit
From the vertical mask period start return period
From 10H before the vertical mask period start return period
The vertical mask period is the return period
The vertical mask period is 9H
Clock run discrimination 1 (2 times)
Clock run discrimination 2 (4 times)
Framing code discrimination 1
Framing code discrimination 2 (A single bad bit is ignored)
Error check enabled (The error check can be turned on or off on
per-byte basis.)
Error check disabled (Applications can select whether data with errors
is held or written for each byte.)
Data hold
Data write (Error bits are set to 0 in VPS mode)
Error check turned on for unused bytes
VPS: bytes 3, 4, and 6 to 10, PDC: bytes 7 to 12
Header 1: bytes 14 to 37, 2: 14 to 29, 3 14 to 21.
Status 1 (3): bytes 7 to 25, status 2 (4) bytes 7 to 35.
Error check turned off for unused bytes
VPS: bytes 3, 4, and 6 to 10, PDC: bytes 7 to 12
Header 1: bytes 14 to 37, 2: 14 to 29, 3 14 to 21.
Status 1 (3): bytes 7 to 25, status 2 (4) bytes 7 to 35.
Notes
CPOUT pin (pin 11) vertical mask
period switching 2
CPOUT pin (pin 11) vertical mask
period switching
Clock run discrimination circuit setting
Framing code discrimination selection
When set to 0: If there are no errors in bytes
for which the error check is turned on, those
bytes will be written to P-S (COM7-9).
When set to 1: Data is written to P-S
regardless of whether or not errors occurred.
When error checking is enabled, specifies the
processing when an error occurs in a byte for
which error checking was turned off
Error check setting for unused data
bytes
Biphase (VPS),
Hamming (PDC),
Odd parity (header)
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5965-11/25

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