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PDF M1A3P1000 Data sheet ( Hoja de datos )
| Número de pieza | M1A3P1000 | |
| Descripción | ProASIC3 Flash Family FPGAs | |
| Fabricantes | Actel Corporation | |
| Logotipo |  |
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ProASIC3 Flash Family FPGAs
with Optional Soft ARM® Support
www.DataSheet4U.cvom1.0
®
Features and Benefits
High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM-enabled ProASIC®3
devices) via JTAG (IEEE 1532–compliant)†
• FlashLock® to Secure FPGA Contents
Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os‡
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
• True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft
Processor Available with or without Debug
ProASIC3 Product Family
ProASIC3 Devices
ARM7 Devices 1
Cortex-M1 Devices 1
A3P015 A3P030 A3P060 A3P125 A3P250
M1A3P250
A3P400
M1A3P400
A3P600
M1A3P600
A3P1000
M7A3P1000
M1A3P1000
System Gates
15 k 30 k 60 k 125 k 250 k
400 k
600 k
1M
Typical Equivalent Macrocells
128 256 512 1,024
–
–
–
–
VersaTiles (D-flip-flops)
384
768 1,536 3,072
6,144
9,216
13,824
24,576
RAM kbits (1,024 bits)
– – 18 36 36 54 108 144
4,608-Bit Blocks
– –48
8
12
24
32
FlashROM Bits
Secure (AES) ISP 2
1k 1k 1k 1k
1k
1k
1k
1k
–
– Yes Yes
Yes
Yes
Yes
Yes
Integrated PLL in CCCs
VersaNet Globals 3
– –11
1
1
1
1
6 6 18 18 18
18
18
18
I/O Banks
2 222
4
4
4
4
Maximum User I/Os
49 81 96 133 157
194
235
300
Package Pins
QFN
VQFP
TQFP
PQFP
FBGA
QN68
QN132
VQ100
QN132
VQ100
TQ144
FG144
QN132
VQ100
TQ144
PQ208
FG144
QN132 5
VQ100
PQ208
FG144/256 5
PQ208
FG144/256/
484
PQ208
FG144/256/
484
PQ208
FG144/256/
484
Notes:
1. Refer to the CoreMP7 datasheet or Cortex-M1 product brief for more information.
2. AES is not available for ARM-enabled ProASIC3 devices.
3. Six chip (main) and three quadrant global networks are available for A3P060 and above.
4. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs handbook.
5. The M1A3P250 device does not support this package.
† A3P015 and A3P030 devices do not support this feature.
February 2008
© 2008 Actel Corporation
‡ Supported only by A3P015 and A3P030 devices.
I
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1 – ProASIC3 Device Family Overview
www.DataSheet4U.com
General Description
ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and
features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3
devices the advantage of being a secure, low-power, single-chip solution that is live at power-up
(LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and
A3P030 devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates,
supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.
ProASIC3 devices support the ARM7 soft IP core and Cortex-M1 devices. The ARM-enabled devices
have Actel ordering numbers that begin with M7A3P (CoreMP7) and M1A3P (Cortex-M1) and do
not support AES decryption.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, flash-based ProASIC3 devices allow all functionality to be live at power-up; no
external boot PROM is required. On-board security mechanisms prevent access to all the
programming information and enable secure remote updates of the FPGA logic. Designers can
perform secure remote in-system reprogramming to support future design iterations and field
upgrades with confidence that valuable intellectual property (IP) cannot be compromised or
copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3
family device architecture mitigates the need for ASIC migration at higher user volumes. This
makes the ProASIC3 family a cost-effective ASIC replacement solution, especially for applications in
the consumer, networking/ communications, computing, and avionics markets.
Security
The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no
vulnerable external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock,
which provides a unique combination of reprogrammability and design security without external
overhead, advantages that only an FPGA with nonvolatile flash programming can offer.
ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed
intellectual property and configuration data. In addition, all FlashROM data in ProASIC3 devices
can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher
encryption standard. The AES standard was adopted by the National Institute of Standards and
Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 devices have a built-in AES
decryption engine and a flash-based AES key that make them the most comprehensive
programmable logic device security solution available today. ProASIC3 devices with AES-based
security allow for secure, remote field updates over public networks such as the Internet, and
ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP
thieves. The contents of a programmed ProASIC3 device cannot be read back, although secure
design verification is possible.
ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the
ARM core must be protected at all times, AES encryption is always on for the core logic, so
bitstreams are always encrypted. There is no user access to encryption for the FlashROM
programming data.
v1.0
1-1
5 Page 
ProASIC3 Device Family Overview
www.DataSheet4U.com
I/Os with Advanced I/O Standards
The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages
(1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards—single-ended
and differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these
banks determines the I/O standards supported.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
• Single-Data-Rate applications
• Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications
ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS.
B-LVDS and M-LVDS can support up to 20 loads.
Part Number and Revision Date
Part Number 51700097-001-1
Revised February 2008
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version
51700097-001-1
51700097-001-0
(January 2008)
v2.2
(July 2007)
Changes in Current Version (v1.0)
This document was divided into two sections and given a version number,
starting at v1.0. The first section of the document includes features, benefits,
ordering information, and temperature and speed grade offerings. The second
section is a device family overview.
This document was updated to include A3P015 device information. QN68 is a
new package that was added because it is offered in the A3P015. The following
sections were updated:
"Features and Benefits"
"ProASIC3 Ordering Information"
"Temperature Grade Offerings"
"ProASIC3 Product Family"
"A3P015 and A3P030" note
"Introduction and Overview"
The "ProASIC3 FPGAs Package Sizes Dimensions" table is new.
In the "ProASIC3 Ordering Information", the QN package measurements were
updated to include both 0.4 mm and 0.5 mm.
In the "General Description" section, the number of I/Os was updated from 288
to 300.
This document was previously in datasheet v2.2. As a result of moving to the
handbook format, Actel has restarted the version numbers. The new version
number is 51700097-001-0.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M1A3P1000.PDF ] | |
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