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PDF EBE11UE6ACSA Data sheet ( Hoja de datos )
| Número de pieza | EBE11UE6ACSA | |
| Descripción | 1GB DDR2 SDRAM SO-DIMM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
www.DataSheet4U.com
1GB DDR2 SDRAM SO-DIMM
EBE11UE6ACSA (128M words × 64 bits, 2 Ranks)
Specifications
• Density: 1GB
• Organization
128M words × 64 bits, 2 ranks
• Mounting 8 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
• Package: 200-pin socket type small outline dual in
line memory module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
Document No. E1045E20 (Ver. 2.0)
Date Published December 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007
1 page  
EBE11UE6ACSA
Serial PD Matrix
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Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0
Number of bytes utilized by module
manufacturer
1 0 0 0 0 0 0 0 80H
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
2 Memory type
0 0 0 0 1 0 0 0 08H
3 Number of row address
0 0 0 0 1 1 0 1 0DH
4 Number of column address
0 0 0 0 1 0 1 0 0AH
5 Number of DIMM ranks
0 1 1 0 0 0 0 1 61H
6 Module data width
0 1 0 0 0 0 0 0 40H
7 Module data width continuation 0 0 0 0 0 0 0 0 00H
8 Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
9
DDR SDRAM cycle time, CL = X
-8E (CL = 5)
0 0 1 0 0 1 0 1 25H
-8G (CL = 6)
0 0 1 0 0 1 0 1 25H
-6E (CL = 5)
0 0 1 1 0 0 0 0 30H
10
SDRAM access from clock (tAC)
-8E, -8G
0 1 0 0 0 0 0 0 40H
-6E 0 1 0 0 0 1 0 1 45H
11 DIMM configuration type
0 0 0 0 0 0 0 0 00H
12 Refresh rate/type
1 0 0 0 0 0 1 0 82H
13 Primary SDRAM width
0 0 0 1 0 0 0 0 10H
14 Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
15 Reserved
0 0 0 0 0 0 0 0 00H
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
1
0
0
0
08H
SDRAM device attributes:
18 /CAS latency
0 0 1 1 1 0 0 0 38H
-8E, -6E
-8G 0 1 1 1 0 0 0 0 70H
19
DIMM Mechanical Characteristics
0 0 0 0 0 0 0 1 01H
20 DIMM type information
0 0 0 0 0 1 0 0 04H
21 SDRAM module attributes
0 0 0 0 0 0 0 0 00H
22 SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
Minimum clock cycle time at
23 CL = X − 1
-8E, -6E (CL = 4)
0 0 1 1 1 1 0 1 3DH
-8G (CL = 5)
0 0 1 1 0 0 0 0 30H
Maximum data access time (tAC) from
24 clock at CL = X − 1
0 1 0 1 0 0 0 0 50H
-8E, -6E (CL = 4)
-8G (CL = 5)
0 1 0 0 0 1 0 1 45H
Minimum clock cycle time at
25 CL = X − 2
-8E, -6E (CL = 3)
0 1 0 1 0 0 0 0 50H
-8G (CL = 4)
0 0 1 1 1 1 0 1 3DH
Comments
128 bytes
256 bytes
DDR2 SDRAM
13
10
2
64
0
SSTL 1.8V
2.5ns*1
2.5ns*1
3.0ns*1
0.4ns*1
0.45ns*1
None.
7.8µs
× 16
None.
0
4,8
8
3, 4, 5
4, 5, 6
3.80mm max.
SO-DIMM
Normal
Weak Driver
50Ω ODT Support
3.75ns*1
3.0ns*1
0.5ns*1
0.45ns*1
5.0ns*1
3.75ns*1
Data Sheet E1045E20 (Ver. 2.0)
5
5 Page 
EBE11UE6ACSA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V)
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Parameter
Symbol
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD2P)
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD3N)
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD2P)
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD3N)
Grade max.
-8E, -8G 480
-6E 440
-8E, -8G 800
-6E 720
-8E, -8G 560
-6E 520
-8E, -8G 880
-6E 800
Precharge power-down
standby current
IDD2P
80
Precharge quiet standby
current
IDD2Q
-8E, -8G 280
-6E 240
Idle standby current
IDD2N
-8E, -8G 320
-6E 280
Active power-down
standby current
IDD3P-F
IDD3P-S
280
160
Active standby current
IDD3N
-8E, -8G 720
-6E 640
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD2P)
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD3N)
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD2P)
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD3N)
-8E, -8G 840
-6E 740
-8E, -8G 1160
-6E 1020
-8E, -8G 840
-6E 740
-8E, -8G 1160
-6E 1020
Unit Test condition
mA
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
mA Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address
mA
bus inputs are STABLE; Slow PDN Exit
Data bus inputs are
MRS(12) = 1
FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
mA
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E1045E20 (Ver. 2.0)
11
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