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PDF EBE11UD8ABFA Data sheet ( Hoja de datos )

Número de pieza EBE11UD8ABFA
Descripción 1GB Unbuffered DDR2 SDRAM DIMM
Fabricantes Elpida Memory 
Logotipo Elpida Memory Logotipo



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No Preview Available ! EBE11UD8ABFA Hoja de datos, Descripción, Manual

DATA SHEET
www.DataSheet4U.com
1GB Unbuffered DDR2 SDRAM DIMM
EBE11UD8ABFA (128M words × 64 bits, 2 Ranks)
Description
The EBE11UD8ABFA is 128M words × 64 bits, 2 ranks
DDR2 SDRAM unbuffered module, mounting 16 pieces
of 512M bits DDR2 SDRAM sealed in FBGA (µBGA)
package. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 4 bits prefetch-
pipelined architecture. Data strobe (DQS and /DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology. Decoupling capacitors are mounted
beside each FBGA (µBGA) on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free
1.8V power supply
Data rate: 533Mbps/400Mbps (max.)
1.8V (SSTL_18 compatible) I/O
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
(Component)
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
7.8µs average periodic refresh interval
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation
Document No. E0365E50 (Ver. 5.0)
Date Published August 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2004

1 page




EBE11UD8ABFA pdf
EBE11UD8ABFA
Serial PD Matrix
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Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 1 0 0 0 08H
Number of row address
0 0 0 0 1 1 1 0 0EH
Number of column address
0 0 0 0 1 0 1 0 0AH
Number of DIMM ranks
0 1 1 0 0 0 0 1 61H
Module data width
0 1 0 0 0 0 0 0 40H
Module data width continuation
0 0 0 0 0 0 0 0 00H
Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
DDR SDRAM cycle time, CL = 5
-5C
0 0 1 1 1 1 0 1 3DH
-4A 0 1 0 1 0 0 0 0 50H
SDRAM access from clock (tAC)
-5C
-4A
0 1 0 1 0 0 0 0 50H
0 1 1 0 0 0 0 0 60H
DIMM configuration type
0 0 0 0 0 0 0 0 00H
Refresh rate/type
1 0 0 0 0 0 1 0 82H
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
Reserved
0 0 0 0 0 0 0 0 00H
DIMM type information
0 0 0 0 0 0 1 0 02H
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
SDRAM device attributes: General 0 0 1 1 0 0 0 0 30H
Minimum clock cycle time at CL = 4
-5C 0 0 1 1 1 1 0 1 3DH
-4A 0 1 0 1 0 0 0 0 50H
Maximum data access time (tAC) from
clock at CL = 4
0 1 0 1 0 0 0 0 50H
-5C
-4A 0 1 1 0 0 0 0 0 60H
Minimum clock cycle time at CL = 3
0 1 0 1 0 0 0 0 50H
-5C, -4A
Maximum data access time (tAC) from
clock at CL = 3
0 1 1 0 0 0 0 0 60H
-5C, -4A
Comments
128 bytes
256 bytes
DDR2 SDRAM
14
10
2
64
0
SSTL 1.8V
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
None.
7.8µs
×8
None.
0
4,8
4
3, 4, 5
0
Unbuffered
Normal
VDD ± 0.1V
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
5.0ns*1
0.6ns*1
Data Sheet E0365E50 (Ver. 5.0)
5

5 Page





EBE11UD8ABFA arduino
EBE11UD8ABFA
DC Characteristics 1 (TC = 0 to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
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Parameter
Symbol
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD2P)
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD3N)
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD2P)
Grade
-5C
-4A
-5C
-4A
-5C
-4A
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD3N)
-5C
-4A
Precharge power-down
standby current
IDD2P
-5C
-4A
-5C
-4A
Precharge quiet standby
current
IDD2Q
-5C
-4A
Idle standby current
IDD2N
-5C
-4A
Active power-down
standby current
-5C
IDD3P-F
-4A
-5C
IDD3P-S
-4A
Active standby current
IDD3N
-5C
-4A
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD2P)
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD3N)
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD2P)
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD3N)
Auto-refresh current
(Another rank is in IDD2P)
IDD5
-5C
-4A
-5C
-4A
-5C
-4A
-5C
-4A
-5C
-4A
Auto-refresh current
(Another rank is in IDD3N)
IDD5
-5C
-4A
max.
960
824
1400
1240
1080
944
1520
1360
160
128
400
320
480
400
640
560
400
320
1040
960
1600
1264
2040
1680
1600
1264
2040
1680
2080
1904
2520
2320
Unit Test condition
mA one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
mA Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address bus
mA
inputs are STABLE;
Slow PDN Exit
Data bus inputs are FLOATING MRS(12) = 1
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
tCK = tCK (IDD);
mA Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
mA Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E0365E50 (Ver. 5.0)
11

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