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PDF EBE10AD4AGFA Data sheet ( Hoja de datos )
| Número de pieza | EBE10AD4AGFA | |
| Descripción | 1GB Registered DDR2 SDRAM DIMM | |
| Fabricantes | Elpida Memory | |
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PRELIMINARY DATA SHEET
www.DataSheet4U.com
1GB Registered DDR2 SDRAM DIMM
EBE10AD4AGFA (128M words × 72 bits, 1 Rank)
Specifications
• Density: 1GB
• Organization
128M words × 72 bits, 1 rank
• Mounting 18 pieces of 512M bits DDR2 SDRAM
sealed in FBGA
• Package: 240-pin socket type dual in line memory
module (DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 667Mbps/533Mbps/400Mbps (max.)
• Four internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
• 1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2K bits EEPROM) for
Presence Detect (PD)
Document No. E0865E11 (Ver. 1.1)
Date Published February 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006
1 page  
EBE10AD4AGFA
Serial PD Matrix
www.DataSheet4U.com
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 1 0 0 0 08H
Number of row address
0 0 0 0 1 1 1 0 0EH
Number of column address
0 0 0 0 1 0 1 1 0BH
Number of DIMM ranks
0 1 1 0 0 0 0 0 60H
Module data width
0 1 0 0 1 0 0 0 48H
Module data width continuation
0 0 0 0 0 0 0 0 00H
Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
DDR SDRAM cycle time, CL = 5
-6E
0 0 1 1 0 0 0 0 30H
-5C 0 0 1 1 1 1 0 1 3DH
-4A 0 1 0 1 0 0 0 0 50H
SDRAM access from clock (tAC)
-6E
-5C
0 1 0 0 0 1 0 1 45H
0 1 0 1 0 0 0 0 50H
-4A 0 1 1 0 0 0 0 0 60H
DIMM configuration type
0 0 0 0 0 1 1 0 06H
Refresh rate/type
1 0 0 0 0 0 1 0 82H
Primary SDRAM width
0 0 0 0 0 1 0 0 04H
Error checking SDRAM width
0 0 0 0 0 1 0 0 04H
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
DIMM Mechanical Characteristics
0 0 0 0 0 0 0 1 01H
DIMM type information
0 0 0 0 0 0 0 1 01H
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
Minimum clock cycle time at CL = 4
-6E, -5C
0
0
1
1
1
1
0
1
3DH
-4A 0 1 0 1 0 0 0 0 50H
Maximum data access time (tAC) from
clock at CL = 4
0 1 0 1 0 0 0 0 50H
-6E, -5C
-4A 0 1 1 0 0 0 0 0 60H
Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0 50H
Maximum data access time (tAC) from
clock at CL = 3
0
1
1
0
0
0
0
0
60H
Minimum row precharge time (tRP) 0 0 1 1 1 1 0 0 3CH
Comments
128 bytes
256 bytes
DDR2 SDRAM
14
11
1
72
0
SSTL 1.8V
3.0ns*1
3.75ns*1
5.0ns*1
0.45ns*1
0.5ns*1
0.6ns*1
ECC, Address/
Command Parity
7.8µs
×4
×4
0
4,8
4
3, 4, 5
4.00mm max.
Registered
Normal
Weak Driver 50Ω
ODT Support
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
5.0ns*1
0.6ns*1
15ns
Preliminary Data Sheet E0865E11 (Ver. 1.1)
5
5 Page 
EBE10AD4AGFA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
www.DataSheet4U.com
Parameter
Operating current
(ACT-PRE)
Symbol Grade
IDD0
-6E
-5C
-4A
max.
2570
2440
2120
Operating current
(ACT-READ-PRE)
IDD1
-6E
-5C
-4A
2920
2760
2430
Precharge power-down
standby current
IDD2P
-6E
-5C
-4A
Precharge quiet standby
current
IDD2Q
-6E
-5C
-4A
750
700
620
1020
970
840
Idle standby current
IDD2N
-6E
-5C
-4A
-6E
IDD3P-F -5C
Active power-down standby
-4A
current
-6E
IDD3P-S -5C
-4A
Active standby current
IDD3N
-6E
-5C
-4A
1200
1060
930
1290
1240
1110
1020
970
840
1850
1720
1580
Operating current
(Burst read operating)
IDD4R
-6E
-5C
-4A
4270
3660
3060
Operating current
(Burst write operating)
-6E
IDD4W -5C
-4A
4090
3660
3060
Unit Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA
CKE is H, /CS is H;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open;
tCK = tCK (IDD);
mA CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and
address bus inputs are
mA
STABLE;
Data bus inputs are
Slow PDN Exit
MRS(12) = 1
FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP
mA (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Preliminary Data Sheet E0865E11 (Ver. 1.1)
11
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