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PDF IDT5T93GL10 Data sheet ( Hoja de datos )

Número de pieza IDT5T93GL10
Descripción 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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IDT5T93GL10
2.5VLVDS1:10GLITCHLESSCLOCKBUFFERTERABUFFERII
2.5V LVDS 1:10
GLITCHLESS CLOCK BUFFER
TERABUFFER™ II
INDUSTRwIAwLwT.EDMaPtaESRhAeeTUt4RUE.cRoAmNGE
IDT5T93GL10
FEATURES:
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 100ps (max)
• High speed propagation delay < 2ns (max)
• Up to 650MHz operation
• Glitchless input clock switching
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input interface
• Selectable differential inputs to ten LVDS outputs
• Power-down mode
• 2.5V VDD
• Available in VFQFPN package
APPLICATIONS:
• Clock distribution
DESCRIPTION:
The IDT5T93GL10 2.5V differential clock buffer is a user-selectable differ-
entialinputtotenLVDSoutputs. ThefanoutfromadifferentialinputtotenLVDS
outputs reduces loading on the preceding driver and provides an efficient clock
distributionnetwork. TheIDT5T93GL10canactasatranslatorfromadifferential
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to
translatetoLVDSoutputs. Theredundantinputcapabilityallowsforaglitchless
change-over from a primary clock source to a secondary clock source.
SelectableinputsarecontrolledbySEL. Duringtheswitchover,theoutputwill
disable low for up to three clock cycles of the previously-selected input clock.
The outputs will remain low for up to three clock cycles of the newly-selected
clock, after which the outputs will start from the newly-selected input. A FSEL
pin has been implemented to control the switchover in cases where a clock
source is absent or is driven to DC levels below the minimum specifications.
The IDT5T93GL10 outputs can be asynchronously enabled/disabled.
Whendisabled,theoutputswilldrivetothevalueselectedbytheGLpin. Multiple
power and grounds reduce noise.
FUNCTIONAL BLOCK DIAGRAM
GL
G1
OUTPUT
CONTROL
Q1
Q1
PD
OUTPUT
Q2
CONTROL
Q2
A1 1
A1
OUTPUT
Q3
CONTROL
Q3
A2
0
OUTPUT
Q4
A2
CONTROL
Q4
SEL
FSEL
G2
OUTPUT
CONTROL
OUTPUT
CONTROL
Q5
Q5
Q6
Q6
OUTPUT
CONTROL
Q7
Q7
OUTPUT
CONTROL
Q8
Q8
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2007 Integrated Device Technology, Inc.
1
OUTPUT
CONTROL
OUTPUT
CONTROL
Q9
Q9
Q10
Q10
JANUARY 2007
DSC 6184/15

1 page




IDT5T93GL10 pdf
IDT5T93GL10
2.5VLVDS1:10GLITCHLESSCLOCKBUFFERTERABUFFERII
INDUSTRwIAwLwT.EDMaPtaESRhAeeTtU4RUE.cRoAmNGE
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL
Symbol
Parameter
Value
Units
VDIF Input Signal Swing(1)
1V
VX Differential Input Signal Crossing Point(2)
750 mV
DH Duty Cycle
50 %
VTHI InputTimingMeasurementReferenceLevel(3)
Crossing Point
V
tR, tF Input Signal Edge Rate(4)
2 V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol
Parameter
Value
Units
VDIF Input Signal Swing(1)
1V
VX Differential Input Signal Crossing Point(2)
900 mV
DH Duty Cycle
50 %
VTHI InputTimingMeasurementReferenceLevel(3)
Crossing Point
V
tR, tF Input Signal Edge Rate(4)
2 V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL (2.5V) AND
LVPECL (3.3V)
Symbol
Parameter
Value
Units
VDIF Input Signal Swing(1)
732 mV
VX Differential Input Signal Crossing Point(2)
LVEPECL
1082 mV
LVPECL
1880
DH Duty Cycle
50 %
VTHI InputTimingMeasurementReferenceLevel(3)
Crossing Point
V
tR, tF Input Signal Edge Rate(4)
2 V/ns
NOTES:
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point levels are specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.
This device meets the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
5

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IDT5T93GL10 arduino
IDT5T93GL10
2.5VLVDS1:10GLITCHLESSCLOCKBUFFERTERABUFFERII
A1 - A1
A2 - A2
FSEL
SEL
Qn - Qn
INDUSTRwIAwLwT.EDMaPtaESRhAeeTtU4RUE.cRoAmNGE
+VDIF
VDIF=0
-VDIF
+VDIF
VDIF=0
-VDIF
VIH
VTHI
VIL
VIH
VTHI
VIL
+VDIF
VDIF=0
-VDIF
Selection of Input While Protecting Against When Opposite Clock Dies
NOTES:
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock.
2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart with the input clock selected by the SEL
pin.
3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output will be driven LOW and will restart with
the input clock selected by the SEL pin.
A1 - A1
+VDIF
VDIF=0
-VDIF
A2 - A2
+VDIF
VDIF=0
-VDIF
VIH
Gx VTHI
VIL
VIH
PD VTHI
VIL
Qn - Qn
+VDIF
VDIF=0
-VDIF
Power Down Timing
NOTES:
1. It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after
asserting PD.
2. The POWER DOWN TIMING diagram assumes that GL is HIGH.
3. It should be noted that during power-down mode, the outputs are both pulled to VDD. In the POWER DOWN TIMING diagram this is shown when Qn - Qn goes to VDIF = 0.
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