|
|
PDF IDT5T93GL06 Data sheet ( Hoja de datos )
| Número de pieza | IDT5T93GL06 | |
| Descripción | 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT5T93GL06 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
IDT5T93GL06
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
2.5V LVDS 1:6 GLITCHLESS
CLOCK BUFFER
TERABUFFER™ II
INDUSTRwIAwLwT.EDMaPtaESRhAeeTtU4RU.EcRoAmNGE
IDT5T93GL06
FEATURES:
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 100ps (max)
• High speed propagation delay < 2ns (max)
• Up to 800MHz operation
• Glitchless input clock switching up to 650MHz
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input interface
• Selectable differential inputs to six LVDS outputs
• Power-down mode
• 2.5V VDD
• Available in VFQFPN package
APPLICATIONS:
• Clock distribution
DESCRIPTION:
The IDT5T93GL06 2.5V differential clock buffer is a user-selectable differ-
entialinputtosixLVDSoutputs. ThefanoutfromadifferentialinputtosixLVDS
outputs reduces loading on the preceding driver and provides an efficient clock
distributionnetwork. TheIDT5T93GL06canactasatranslatorfromadifferential
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to
translatetoLVDSoutputs. Theredundantinputcapabilityallowsforaglitchless
change-over from a primary clock source to a secondary clock source up to
650MHz. Selectable inputs are controlled by SEL. During the switchover, the
output will disable low for up to three clock cycles of the previously-selected input
clock. The outputs will remain low for up to three clock cycles of the newly-
selected clock, after which the outputs will start from the newly-selected input.
A FSEL pin has been implemented to control the switchover in cases where a
clock source is absent or is driven to DC levels below the minimum specifications.
The IDT5T93GL06 outputs can be asynchronously enabled/disabled.
Whendisabled,theoutputswilldrivetothevalueselectedbytheGLpin. Multiple
power and grounds reduce noise.
FUNCTIONAL BLOCK DIAGRAM
GL
G
PD
A1
A1
A2
A2
SEL
FSEL
1
0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2003 Integrated Device Technology, Inc.
1
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
OCTOBER 2003
DSC-6183/8
1 page  
IDT5T93GL06
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
INDUSTRwIAwLwT.EDMaPtaESRhAeeTtU4RUE.cRoAmNGE
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL
Symbol
Parameter
Value
Units
VDIF Input Signal Swing(1)
1V
VX Differential Input Signal Crossing Point(2)
750 mV
DH Duty Cycle
50 %
VTHI InputTimingMeasurementReferenceLevel(3)
Crossing Point
V
tR, tF Input Signal Edge Rate(4)
2 V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol
Parameter
Value
Units
VDIF Input Signal Swing(1)
1V
VX Differential Input Signal Crossing Point(2)
900 mV
DH Duty Cycle
50 %
VTHI InputTimingMeasurementReferenceLevel(3)
Crossing Point
V
tR, tF Input Signal Edge Rate(4)
2 V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL (2.5V) AND
LVPECL (3.3V)
Symbol
Parameter
Value
Units
VDIF Input Signal Swing(1)
732 mV
VX Differential Input Signal Crossing Point(2)
LVEPECL
1082 mV
LVPECL
1880
DH Duty Cycle
50 %
VTHI InputTimingMeasurementReferenceLevel(3)
Crossing Point
V
tR, tF Input Signal Edge Rate(4)
2 V/ns
NOTES:
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point levels are specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.
This device meets the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
5
5 Page 
IDT5T93GL06
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
A1 - A1
A2 - A2
SEL
FSEL
INDUSTRwIAwLwT.EDMaPtaESRhAeeTtU4RUE.cRoAmNGE
+VDIF
VDIF=0
-VDIF
+VDIF
VDIF=0
-VDIF
VIH
VTHI
VIL
VIH
VTHI
VIL
Qn - Qn
+VDIF
VDIF=0
-VDIF
FSEL Operation to Protect Against When Opposite Clock Dies
NOTES:
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock.
2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart with the input clock selected by the SEL
pin.
3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output will be driven LOW and will restart with
the input clock selected by the SEL pin.
A1 - A1
A2 - A2
FSEL
SEL
Qn - Qn
+VDIF
VDIF=0
-VDIF
+VDIF
VDIF=0
-VDIF
VIH
VTHI
VIL
VIH
VTHI
VIL
+VDIF
VDIF=0
-VDIF
Selection of Input While Protecting Against When Opposite Clock Dies
NOTES:
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock.
2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart with the input clock selected by the SEL
pin.
3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output will be driven LOW and will restart with
the input clock selected by the SEL pin.
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet IDT5T93GL06.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT5T93GL02 | 2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER II | Integrated Device Technology |
| IDT5T93GL04 | 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER II | Integrated Device Technology |
| IDT5T93GL06 | 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II | Integrated Device Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |