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PDF IDT5T93GL04 Data sheet ( Hoja de datos )
| Número de pieza | IDT5T93GL04 | |
| Descripción | 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER II | |
| Fabricantes | Integrated Device Technology | |
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2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER
TERABUFFER™ II
IDT5T93GL04
General Description
Features
The IDT5T93GL04 2.5V differential clock buffer is a
user-selectable differential input to four LVDS outputs. The fanout
from a differential input to four LVDS outputs reduces loading on
the preceding driver and provides an efficient clock distribution
network. The IDT5T93GL04 can act as a translator from a
differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V
LVTTL input can also be used to translate to LVDS outputs. The
redundant input capability allows for a glitchless change-over from
a primary clock source to a secondary clock source up to 450MHz.
Selectable inputs are controlled by SEL. During the switchover,
the output will disable low for up to three clock cycles of the
previously-selected input clock. The outputs will remain low for up
to three clock cycles of the newly-selected clock, after which the
outputs will start from the newly-selected input. A FSEL pin has
been implemented to control the switchover in cases where a
clock source is absent or is driven to DC levels below the minimum
specifications.
The IDT5T9304 outputs can be asynchronously enabled/disabled.
When disabled, the outputs will drive to the value selected by the
GL pin. Multiple power and grounds reduce noise.
• Guaranteed low skew: <50ps (maximum)
• Very low duty cycle distortion: <100ps (maximum
• High speed propagation delay: <2.2ns (maximum)
• Up to 450MHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML or LVDS input interface
• Selectable differential inputs to four LVDS outputs
• Power-down mode
• At power-up, FSEL should be LOW
• 2.5V VDD
• -40°C to 85°C ambient operating temperature
• Available in TSSOP package
Applications
• Clock distribution
Pin Assignment
GND
PD
FSEL
VDD
Q1
Q1
Q2
Q2
VDD
SEL
G
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 A2
23 A2
22 GND
21 VDD
20 Q3
19 Q3
18 Q4
17 Q4
16 VDD
15 GL
14 A1
13 A1
24-Lead TSSOP
4.4mm x 7.8mm x 1.0mm package body
G Package
Top View
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
1
IDT5T93GL04 REV. A JULY 10, 2007
1 page  
IDT5T93GL04
2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
www.DataSheet4U.com
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics(1), TA = -40°C to 85°C
Symbol Parameter
Test Conditions
IDDQ
Quiescent VDD
Power Supply Current
VDD = Max.,
All Input Clocks = LOW(2); Outputs enabled
ITOT
Total Power
VDD Supply Current
IPD
Total Power Down
Supply Current
VDD = 2.7V;
FREFERENCE Clock = 450MHz
PD = LOW
Minimum
Typical(2)
Maximum
240
250
5
NOTE 1: These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.
NOTE 2: The true input is held LOW and the complementary input is held HIGH.
Units
mA
mA
mA
Table 4B. LVTTL DC Characteristics(1), TA = -40°C to 85°C
Symbol Parameter
Test Conditions
IIH
IIL
VIK
VIN
VIH
VIL
VTHI
VREF
Input High Current
Input Low Current
Clamp Diode Voltage
DC Input Voltage
DC Input High Voltage
DC Input Low Voltage
DC Input Threshold Crossing Voltage
Single-Ended Reference Voltage (3)
VDD = 2.7V
VDD = 2.7V
VDD = 2.3V, IIN = -18mA
3.3V LVTTL
2.5V LVTTL
Minimum
-0.3
1.7
NOTE 1: See Recommended Operating Range table.
NOTE 2: Typical values are at VDD = 2.5V, +25°C ambient.
NOTE 3: For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage.
Typical(2)
-0.7
VDD/2
1.65
1.25
Maximum
±5
±5
-1.2
3.6
0.7
Units
µA
µA
V
V
V
V
V
V
V
Table 4C. Differential DC Characteristics(1), TA = -40°C to 85°C
Symbol Parameter
Test Conditions
IIH
IIL
VIK
VIN
VDIF
VCM
Input High Current
Input Low Current
Clamp Diode Voltage
DC Input Voltage
DC Differential Voltage(3)
DC Common Mode Input Voltage
VDD = = 2.7V
VDD = = 2.7V
VDD = 2.3V, IIN = -18mA
Minimum Typical(2)
-0.7
-0.3
0.1
0.05
Maximum
±5
±5
-1.2
3.6
VDD
Units
µA
µA
V
V
V
V
NOTE 1: See Recommended Operating Range table.
NOTE 2: VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and
VCP is the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW
input. The AC differential voltage must be achieved to guarantee switching to a new state.
NOTE 3: VCM specifies the maximum allowable range of (VTR + VCP) /2.
NOTE 4: Typical values are at VDD = 2.5V, +25°C ambient.
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
5
IDT5T93GL04 REV. A JULY 10, 2007
5 Page 
IDT5T93GL04
2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
FSEL Operation for When Opposite Clock Dies
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1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state.
When this happens, the FSEL pin should be asserted in order to force selection of the new input clock. The output clock will start up after
a number of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that
the unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.
Selection of Input While Protecting Against When Opposite Clock Dies
A1 - A1
A2 - A2
FSEL
SEL
+VDIF
VDIF=0
-VDIF
+VDIF
VDIF=0
-VDIF
VIH
VTHI
VIL
VIH
VTHI
VIL
Qn - Qn
+VDIF
VDIF=0
-VDIF
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock.
2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart
with the input clock selected by the SEL pin.
3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output
will be driven LOW and will restart with the input clock selected by the SEL pin.
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
11
IDT5T93GL04 REV. A JULY 10, 2007
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet IDT5T93GL04.PDF ] | |
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