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PDF IDT5T905 Data sheet ( Hoja de datos )

Número de pieza IDT5T905
Descripción 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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IDT5T905
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER
2.5V SINGLE DATA RATE
1:5 CLOCK BUFFER
TERABUFFER™
INDUSTRwIAwLwT.EDMaPtaESRhAeeTtU4RUE.cRoAmNGE
IDT5T905
FEATURES:
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion
• High speed propagation delay < 2.5ns. (max)
• Up to 250MHz operation
• Very low CMOS power levels
• 1.5V VDDQ for HSTL interface
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input
interface
• Selectable differential or single-ended inputs and five single-
ended outputs
• 2.5V VDD
• Available in TSSOP package
APPLICATIONS:
• Clock and signal distribution
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT5T905 2.5V single data rate (SDR) clock buffer is a user-selectable
single-ended or differential input to five single-ended outputs buffer built on
advancedmetalCMOStechnology. TheSDRclockbufferfanoutfromasingle
or differential input to five single-ended outputs reduces the loading on the
preceding driver and provides an efficient clock distribution network. The
IDT5T905 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V
LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL,
1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input
signals that may be hard-wired to appropriate high-mid-low levels. Multiple
power and grounds reduce noise.
TxS
GL
G
OUTPUT
CONTROL
Q1
RxS
A
A/VREF
OUTPUT
CONTROL
OUTPUT
CONTROL
Q2
Q3
OUTPUT
CONTROL
Q4
OUTPUT
CONTROL
Q5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2003 Integrated Device Technology, Inc.
1
FEBRUARY 2003
DSC-5942/25

1 page




IDT5T905 pdf
IDT5T905
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER
INDUSTRwIAwLwT.EDMaPtaESRhAeeTtU4RUE.cRoAmNGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR HSTL(1)
Symbol
Parameter
Input Characteristics
IIH Input HIGH Current(9)
IIL Input LOW Current(9)
VIK Clamp Diode Voltage
VIN DC Input Voltage
VDIF DC Differential Voltage(2,8)
VCM DC Common Mode Input Voltage(3,8)
VIH DC Input HIGH(4,5,8)
VIL DC Input LOW(4,6,8)
VREF Single-EndedReferenceVoltage(4,8)
Output Characteristics
VOH Output HIGH Voltage
VOL OutputLOWVoltage
Test Conditions
VDD = 2.6V
VI = VDDQ/GND
VDD = 2.6V
VI = GND/VDDQ
VDD = 2.4V, IIN = -18mA
IOH = -8mA
IOH = -100µA
IOL = 8mA
IOL = 100µA
Min. Typ.(7)
- 0.3
0.2
680
VREF + 100
- 0.7
750
750
VDDQ - 0.4
VDDQ - 0.1
Max
±5
±5
- 1.2
+3.6
900
VREF - 100
0.4
0.1
Unit
µA
V
V
V
mV
mV
mV
mV
V
V
V
V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be
referenced.
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
POWER SUPPLY CHARACTERISTICS FOR HSTL OUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
IDDQ Quiescent VDD Power Supply Current
VDDQ = Max., Reference Clock = LOW(3)
20
Outputs enabled, All outputs unloaded
IDDQQ
Quiescent VDDQ Power Supply Current
VDDQ = Max., Reference Clock = LOW(3)
0.1
Outputs enabled, All outputs unloaded
IDDD Dynamic VDD Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
10
Current per Output
IDDDQ
Dynamic VDDQ Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
15
Current per Output
ITOT Total Power VDD Supply Current
VDDQ = 1.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF
20
VDDQ = 1.5V, FREFERENCE CLOCK = 250MHz, CL = 15pF
25
ITOTQ Total Power VDDQ Supply Current
VDDQ = 1.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF
15
VDDQ = 1.5V, FREFERENCE CLOCK = 250MHz, CL = 15pF
30
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Max
30
0.3
20
30
30
40
30
60
Unit
mA
mA
µA/MHz
µA/MHz
mA
mA
5

5 Page





IDT5T905 arduino
IDT5T905
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER
INDUSTRwIAwLwT.EDMaPtaESRhAeeTtU4RUE.cRoAmNGE
POWER SUPPLY CHARACTERISTICS FOR 1.8V LVTTL OUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
IDDQ Quiescent VDD Power Supply Current
VDDQ = Max., Reference Clock = LOW(3)
20
Outputs enabled, All outputs unloaded
IDDQQ
Quiescent VDDQ Power Supply Current
VDDQ = Max., Reference Clock = LOW(3)
0.1
Outputs enabled, All outputs unloaded
IDDD Dynamic VDD Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
20
Current per Output
IDDDQ
Dynamic VDDQ Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
20
Current per Output
ITOT Total Power VDD Supply Current
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF
20
VDDQ = 1.8V, FREFERENCE CLOCK = 200MHz, CL = 15pF
30
ITOTQ Total Power VDDQ Supply Current
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF
20
VDDQ = 1.8V, FREFERENCE CLOCK = 200MHz, CL = 15pF
45
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Max
30
0.3
30
30
30
40
40
80
Unit
mA
mA
µA/MHz
µA/MHz
mA
mA
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol
Parameter
Value
Units
VDIF Input Signal Swing(1)
VDDI V
VX Differential Input Signal Crossing Point(2)
VDDI/2
mV
VTHI InputTimingMeasurementReferenceLevel(3)
Crossing Point
V
tR, tF Input Signal Edge Rate(4)
1.8 V/ns
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable
results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions.
2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the
VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol
Parameter
Value
Units
VIH Input HIGH Voltage(1)
VDDI V
VIL Input LOW Voltage
0V
VTHI InputTimingMeasurementReferenceLevel(2)
VDDI/2
mV
tR, tF Input Signal Edge Rate(3)
2 V/ns
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.
2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
11

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