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PDF LM2833 Data sheet ( Hoja de datos )

Número de pieza LM2833
Descripción 1.5MHz/3MHz 3.0A Step-Down DC-DC Switching Regulator
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! LM2833 Hoja de datos, Descripción, Manual

January 13, 2009
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LM2833
1.5MHz/3MHz 3.0A Step-Down DC-DC Switching Regulator
General Description
The LM2833 regulator is a monolithic, high frequency, PWM
step-down DC/DC converter available in a 10-pin LLP or eM-
SOP package. It contains all the active functions to provide
local DC/DC conversion with fast transient response and ac-
curate regulation in the smallest possible PCB area. With a
minimum of external components, the LM2833 is easy to use.
The ability to drive 3.0A loads with an internal 56 mPMOS
switch using state-of-the-art 0.5µm BiCMOS technology re-
sults in the best power density available. The world-class
control circuitry allows on-times as low as 30ns, thus sup-
porting exceptionally high frequency conversion over the en-
tire 3V to 5.5V input operating range down to the minimum
output voltage of 0.6V. Switching frequency is internally set
to 1.5MHz or 3.0MHz, allowing the use of extremely small
surface mount inductors and capacitors. Even though the op-
erating frequency is high, efficiencies up to 93% are easy to
achieve. External shutdown is included, featuring an ultra-low
stand-by current of 300nA. The LM2833 utilizes peak current-
mode control and internal compensation to provide high-
performance regulation over a wide range of operating
conditions. Additional features include internal soft-start cir-
cuitry to reduce inrush current, cycle-by-cycle current limit,
frequency foldback, thermal shutdown, and output over-volt-
age protection.
Features
Input voltage range of 3.0V to 5.5V
Output voltage range of 0.6V to 4.5V
Tiny eMSOP-10 or LLP-10 package
3.0A steady-state output current
High switching frequencies
1.5MHz (LM2833X)
3.0MHz (LM2833Z)
Enable pin
56mPMOS switch
0.6V, 2% internal voltage reference over line and
temperature
Internal soft-start
Internally compensated peak current-mode control
Cycle-by-cycle current limit and thermal shutdown
Frequency foldback protection
Input voltage UVLO (Under-voltage lockout)
Output over-voltage protection
Applications
Multimedia Set Top Box
Broadband Communications
Core Power in HDDs
Data Acquisition/Telemetry
USB Powered Devices
DSL Modems
Typical Application Circuit
30013201
© 2009 National Semiconductor Corporation 300132
30013212
www.national.com

1 page




LM2833 pdf
Typical Performance Characteristics
Unless otherwise specified, VIN = 5V and TA = 25°C.
Efficiency vs Load Current - "LM2833X" and "LM2833Z"
www.DataSheet4U.com
Efficiency vs Load Current - "LM2833X"
30013213
Efficiency vs Load Current - "LM2833Z"
30013214
Oscillator Frequency vs Temperature - "LM2833X"
30013215
Oscillator Frequency vs Temperature - "LM2833Z"
30013225
Current Limit vs Temperature
30013226
5
30013227
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LM2833 arduino
30013260
FIGURE 3. Startup Response to VIN
FREQUENCY FOLDBACK
The LM2833 uses frequency foldback towhewlpwl.iDmaittaswShitechetc4uUr-.com
rent and power dissipation during start-up, short-circuit and
over load conditions by sensing if the feedback voltage is be-
low 0.32V (typical). The LM2833 will reduce the switching
frequency from the nominal fixed value (1.5MHz or 3.0MHz)
down to 400kHz (LM2833X) or 800kHz (LM2833Z) when the
feedback voltage drops to 0V. See the Frequency Foldback
plot in the Typical Performance Characteristics section.
LOAD STEP RESPONSE
The LM2833 has a fixed internal loop compensation, which
results in a small-signal loop bandwidth highly related to the
output voltage level. In general, the loop bandwidth at low
voltage is larger than at high voltage due to the increased
overall loop gain. The limited bandwidth at high output voltage
may pose a challenge when loop step response is concerned.
In this case, one effective approach to improving loop step
response is to add a feed-forward capacitor (CFF) in the range
of 27nF to 100nF in parallel with the upper feedback resistor
(assuming the lower feedback resistor is 2k), as shown in
Figure 6. The feed-forward capacitor introduces a zero-pole
pair which helps compensate the loop. The position of the
zero-pole pair is a function of the feedback resistors and ca-
pacitor:
30013261
FIGURE 4. Startup Response to VIN with CFF
Note the factor in parenthesis is the ratio of the output voltage
to the feedback voltage. As the output voltage gets close to
0.6V, the pole moves towards the zero, tending to cancel it
out. Consequently, adding CFF will have less effect on the step
response at lower output voltages.
As an example, Figure 8 shows that at the output voltage of
3.3V, a 47nF of CFF can boost the loop bandwidth to 117kHz,
from the original 23kHz as shown in Figure 7. Correspond-
ingly, the responses to a load step between 0.3A and 3A
without and with CFF are shown in Figure 9 and Figure 10
respectively. The higher loop bandwidth as a result of CFF re-
duces the total output excursion by more than half.
Aside from the above approach, increasing the output capac-
itance is generally also effective to reduce the excursion in
output voltage caused by a load step. This approach remains
valid for applications where the desired output voltages are
close to the feedback voltage.
30013262
FIGURE 5. Startup Response to VIN with 100µs rise time
11
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