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PDF 23A640 Data sheet ( Hoja de datos )

Número de pieza 23A640
Descripción 64K SPI Bus Low-Power Serial SRAM
Fabricantes Microchip Technology 
Logotipo Microchip Technology Logotipo



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No Preview Available ! 23A640 Hoja de datos, Descripción, Manual

23A640/23K640
64K SPI Bus Low-Power Serial SRAM
Device Selection Table
Part Number
23K640
23A640
VCC Range
2.7-3.6V
1.5-1.95V
Page Size
32 Byte
32 Byte
Features:
• Max. Clock 20 MHz
• Low-Power CMOS Technology:
- Read Current: 3 mA at 1 MHz
- Standby Current: 4 A Max. at +85°C
• 8192 x 8-bit Organization
• 32-Byte Page
• HOLD pin
• Flexible Operating modes:
- Byte read and write
- Page mode (32 Byte Page)
- Sequential mode
• Sequential Read/Write
• High Reliability
• Temperature Ranges Supported:
- Industrial (I):
-40C to +85C
- Automotive (E):
-40C to +125C
• Pb-Free and RoHS Compliant, Halogen Free
Pin Function Table
Name
Function
CS
SO
VSS
SI
SCK
HOLD
VCC
Chip Select Input
Serial Data Output
Ground
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
Temp. Ranges
I, E
I
Packages
P, SN, ST
P, SN, ST
Description:
The Microchip Technology Inc. 23X640 are 64 Kbit
Serial SRAM devices. The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
The 23X640 is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packaging including 8-lead TSSOP.
Package Types (not to scale)
PDIP/SOIC/TSSOP
(P, SN, ST)
CS 1
SO 2
NC 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
2008-2011 Microchip Technology Inc.
DS22126E-page 1

1 page




23A640 pdf
23A640/23K640
FIGURE 1-1: HOLD TIMING
CS
SCK
SO
n+2
16
15
n+1
17
n
15 16
18
High-Impedance
n
Don’t Care
SI
n+2
n+1
n
5
n
HOLD
n-1
n-1
FIGURE 1-2: SERIAL INPUT TIMING
CS
SCK
SI
SO
2
56
MSB in
7
High-Impedance
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
SI
9 10
12
MSB out
Don’t Care
8
13
4
11
3
LSB in
3
14
LSB out
2008-2011 Microchip Technology Inc.
DS22126E-page 5

5 Page





23A640 arduino
23A640/23K640
2.5 Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time. The STATUS register is
formatted as follows:
TABLE 2-2: STATUS REGISTER
7 6 54321
W/R W/R – – – – –
MODE MODE 0 0 0 0 1
W/R = writable/readable.
0
W/R
HOLD
The mode bits indicate the operating mode of the
SRAM. The possible modes of operation are:
0 0 = Byte mode (default operation)
1 0 = Page mode
0 1 = Sequential mode
1 1 = Reserved
Write and read commands are shown in Figure 2-7 and
Figure 2-8.
The HOLD bit enables the Hold pin functionality. It must
be set to a ‘0’ before HOLD pin is brought low for HOLD
function to work properly. Setting HOLD to ‘1’ disables
feature.
Bits 2 through 5 are reserved and should always be set
to ‘0’. Bit 1 will read back as ‘1’ but should always be
written as ‘0’.
See Figure 2-7 for the RDSR timing sequence.
FIGURE 2-7: READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
0 00 00 1 01
High-Impedance
Data from STATUS Register
7 6 54 3 2 10
2008-2011 Microchip Technology Inc.
DS22126E-page 11

11 Page







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