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PDF C8051T600 Data sheet ( Hoja de datos )

Número de pieza C8051T600
Descripción (C8051T600 - C8051T605) Mixed Signal OTP EPROM MCU Family
Fabricantes Silicon Laboratories　
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No Preview Available ! C8051T600 Hoja de datos, Descripción, Manual

C8051T600/1/2/3/4/5
www.DataSheet4U.com
Mixed Signal OTP EPROM MCU Family
Analog Peripherals
- 10-Bit Analog to Digital Converter
• Up to 500 ksps
• Up to 8 external inputs
• VREF from external pin, VDD, or internal regulator
• Built-in temperature sensor
• External conversion start input option
- Comparator
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
• Low current (< 0.5 µA)
Memory
- 256 bytes internal data RAM
- 8, 4 or 2 kB one time programmable code memory
On-Chip Debug
- C8051F300 can be used as in-system code devel-
opment platform; complete development kit avail-
able
- On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug
Supply Voltage 1.8 to 3.6 V
- On-chip LDO regulator for core supply
- Typical operating current: 5.0 mA @ 25 MHz
- Typical stop mode current (regulator off): <0.1 µA
- Built-in brown-out detector
High Speed 8051 µC Core
- Pipe-lined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- 25 MIPS peak throughput with 25 MHz clock
- Expanded interrupt handler
Digital Peripherals
- 8 port I/O; All 5 V tolerant with high sink current
- Hardware enhanced UART and SMBus™ serial
ports
- Three general purpose 16-bit counter/timers
- 16-Bit programmable counter array (PCA) with three
capture/compare modules
• 8 or 16-bit PWM
• Rising / falling edge capture
• Frequency output
• Software timer
Clock Sources
- Internal oscillator: 24.5 MHz with ±2% accuracy
supports UART operation
- External oscillator: RC, Single Capacitor, or CMOS
Clock Modes
- Can switch between clock sources on-the-fly; useful
in power saving modes
Temperature Range: –40 to +85 °C
11-Pin QFN or 14-Pin SOIC Package
- QFN Size = 3 x 3 mm
ANALOG
PERIPHERALS
A 10-bit
M
U
500 ksps
X ADC
TEMP
SENSOR
+
C8051T600/2/4
-
VOLTAGE
COMPARATOR
DIGITAL I/O
UART
SMBus
PCA
Timer 0
Timer 1
Timer 2
CALIBRATED PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
2/4/8 kB
OTP EPROM
12
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR WDT
Rev. 0.5 2/07
Copyright © 2007 by Silicon Laboratories
C8051T60x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

1 page




C8051T600 pdf
C8051T600/1/2/3/4/5
www.DataSheet4U.com
14.4.3.Data Register ......................................................................................... 116
14.5.SMBus Transfer Modes.................................................................................. 117
14.5.1.Master Transmitter Mode ....................................................................... 117
14.5.2.Master Receiver Mode ........................................................................... 118
14.5.3.Slave Receiver Mode ............................................................................. 119
14.5.4.Slave Transmitter Mode ......................................................................... 120
14.6.SMBus Status Decoding................................................................................. 120
15. UART0.................................................................................................................... 123
15.1.Enhanced Baud Rate Generation................................................................... 124
15.2.Operational Modes ......................................................................................... 125
15.2.1.8-Bit UART ............................................................................................. 125
15.2.2.9-Bit UART ............................................................................................. 126
15.3.Multiprocessor Communications .................................................................... 126
16. Timers.................................................................................................................... 131
16.1.Timer 0 and Timer 1 ....................................................................................... 131
16.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 131
16.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 133
16.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 133
16.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 134
16.2.Timer 2 .......................................................................................................... 139
16.2.1.16-bit Timer with Auto-Reload................................................................ 139
16.2.2.8-bit Timers with Auto-Reload................................................................ 140
17. Programmable Counter Array ............................................................................. 143
17.1.PCA Counter/Timer ........................................................................................ 144
17.2.Capture/Compare Modules ............................................................................ 145
17.2.1.Edge-triggered Capture Mode................................................................ 146
17.2.2.Software Timer (Compare) Mode........................................................... 147
17.2.3.High Speed Output Mode....................................................................... 148
17.2.4.Frequency Output Mode ........................................................................ 149
17.2.5.8-Bit Pulse Width Modulator Mode......................................................... 150
17.2.6.16-Bit Pulse Width Modulator Mode....................................................... 151
17.3.Watchdog Timer Mode ................................................................................... 151
17.3.1.Watchdog Timer Operation .................................................................... 152
17.3.2.Watchdog Timer Usage ......................................................................... 153
17.4.Register Descriptions for PCA........................................................................ 154
18. Revision Specific Behavior ................................................................................. 159
18.1.Revision Identification..................................................................................... 159
18.2.SAR Clock Maximum...................................................................................... 160
18.3.VDD Monitor Oscillation .................................................................................. 160
19. C2 Interface ........................................................................................................... 161
19.1.C2 Interface Registers.................................................................................... 161
19.2.C2 Pin Sharing ............................................................................................... 166
Contact Information.................................................................................................. 168
Rev. 0.5
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C8051T600 arduino
C8051T600/1/2/3/4/5
www.DataSheet4U.com
List of Registers
SFR Definition 5.1. TOFFH: Temperature Offset Measurement High Byte . . . . . . . . . 34
SFR Definition 5.2. TOFFL: Temperature Offset Measurement Low Byte . . . . . . . . . . 35
SFR Definition 5.3. AMX0SL: AMUX0 Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . 39
SFR Definition 5.4. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SFR Definition 5.5. ADC0H: ADC0 Data Word High Byte . . . . . . . . . . . . . . . . . . . . . . 40
SFR Definition 5.6. ADC0L: ADC0 Data Word Low Byte . . . . . . . . . . . . . . . . . . . . . . . 40
SFR Definition 5.7. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte . . . . . . . . . . . . . . . . . . 43
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte . . . . . . . . . . . . . . . . . . 43
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte . . . . . . . . . . . . . . . . . . . 43
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte . . . . . . . . . . . . . . . . . . . . 43
SFR Definition 6.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 51
SFR Definition 8.1. REG0CN: Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . . . 54
SFR Definition 9.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SFR Definition 9.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SFR Definition 9.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SFR Definition 9.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SFR Definition 9.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 9.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 9.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SFR Definition 9.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 75
SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 76
SFR Definition 9.11. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 77
SFR Definition 9.12. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SFR Definition 10.1. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 12.1. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 12.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 12.3. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 13.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 100
SFR Definition 13.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 101
SFR Definition 13.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 102
SFR Definition 13.4. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SFR Definition 13.5. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SFR Definition 13.6. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 103
SFR Definition 14.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 112
SFR Definition 14.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
SFR Definition 14.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SFR Definition 15.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SFR Definition 15.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 129
Rev. 0.5
11

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