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PDF LC72709W Data sheet ( Hoja de datos )

Número de pieza LC72709W
Descripción FM Multiplex Reception IC for Mobile Systems
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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No Preview Available ! LC72709W Hoja de datos, Descripción, Manual

Ordering number : EN5876
CMOS IC
LC72709E, 72709W
FM Multiplex Reception IC for Mobile Systems
Overview
The LC72709E is a data demodulation IC for receiving
FM multiplex broadcasts for mobile receivers in the
DARC format. This IC includes a built-in bandpass filter
that extracts the DARC signal from the FM baseband
signal. Since this IC supports all of the FM multiplex
broadcast frame structures (methods A, A', B, and C) from
the ITU-R recommendations, it is optimal for use in radios
for worldwide use that support FM multiplex reception.
Functions
• SCF-based adjustment-free 76-kHz bandpass filter
• Support for the FM multiplex broadcast frame structures
(methods A, B, and C) using serial data control.
• MSK delay detection circuit based on a 1T delay
• Error correction function based on a 2T delay (in the
MSK detector stage)
• Digital PLL based clock regeneration circuit
• Shift-register type 1T and 2T delay circuits
• Block and frame synchronization detection circuit
• Function for setting the number of allowable BIC errors,
the number of synchronization protection.
• Error correction using (272, 190) codes
• Layer 4 CRC code checking circuit
• On-chip frame memory and memory control circuit for
vertical correction
• 7.2-MHz crystal oscillator circuit
• Two power saving functions (Standby and EC stop)
Package Dimensions
unit: mm
3148-QIP44MA
[LC72709E]
unit: mm
3190-SQFP64
[LC72709W]
SANYO: QIP44MA
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO: SQFP64
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
71598RM (OT) No. 5876-1/16

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LC72709W pdf
Continued from preceding page.
Pin No.
LC72709E LC72709W Pin Name
LC72709E, 72709W
Function
I/O
35 51
VREF
Reference voltage output (Vdda/2)
Output
Circuit type
37 54
34 50
2, 10, 24 3, 14, 35,
11,23, 43 15, 34, 62
VDDA
VSSA
VDDD
VSSD
Analog system power supply
Analog system ground
Digital system power supply (4.5 to 5.5 V)
Digital system ground
1, 4, 8,
12, 16,
17, 21,
25, 28,
32, 33,
37, 41,
45, 48,
49, 53,
56, 60,
64
NC Not connection
Note: A capacitor of at least 2000 pF must be inserted between VDDD and VSSD when using this IC.
Data I/O Techniques
• CCB Technique
Sanyo audio ICs input and output data using the Sanyo CCB (computer control bus) standard, which is a serial bus
format. This IC uses an 8-bit address CCB and uses the following addresses.
Address
I/O mode
B0 B1 B2 B3 A0 A1 A2 A3
Function
Input
0 1 0 1 1 1 1 1 16-bit control data input
Output
1 1 0 1 1 1 1 1 Data output for the input clock (CL)
Input
0 0 1 1 1 1 1 1 Data input (in 8-bit units) for the layer 4 CRC check circuit
• Data Input Timing
• Data Output Timing
Internal data latching
A10595
A10596
Note:The DO pin is normally left open.
Since the DO pin is an n-channel open drain pin, the time required for the data to change from the low level to the high level depends on the value of
the pull-up resistor.
No. 5876-5/16

5 Page





LC72709W arduino
LC72709E, 72709W
• To prevent unnecessary error correction, the vertical correction is not applied to packets that were fully corrected by
horizontal correction or to packets that had no errors.
• Vertical correction is executed when all packet data in the object data was received while frame synchronization was
established and not all of the packet (block) data was corrected by horizontal correction. Vertical correction is not
performed if a whole frame of data with no errors is received, or if the frame was not synchronized. Also, the
corresponding post-vertical correction output data is not output.
• All data can be output, regardless of the correction complete/incomplete, synchronized/unsynchronized reception,
data/packet status or other conditions by setting bit 5 (INT) in the control register to 1. However, there also are cases
where the vertical correction output data is not output as described above.
CPU Interface Basic Restrictions
To save internal memory, this IC uses the smallest possible output buffer. Since the data that the IC receives is written to
memory without any breaks, if data readout is delayed post-correction data that should be read out will be overwritten by
the next data to be output. The output timings in this IC for post-correction (horizontal and vertical) data are stipulated as
follows.
• When preparation of the output data has completed, the IC issues a transfer request by setting the INT pin low.
• For data output, there are periods in which only horizontal data can be output and periods in which both horizontal data
and vertical data can be output.
• Data transfers must be completed within about 9 ms after the INT pin goes low. For periods in which only post-
horizontal correction data can be output, data can be transferred over a period of about 18 ms. Even if the CPU is in the
midst of a read operation, the next output data will be written to the output buffer after the specified period elapses.
• Only one block of data can be read for a single transfer request (INT) for both vertical and horizontal correction. After
vertical correction processing completes, the post-vertical correction data is output in order starting with block number
1, and the parity block data is not output.
Only horizontal
data output
Horizontal and
vertical data output
Horizontal data
output period
Horizontal data
output period
Period when
data cannot be
guaranteed
Vertical data output period
Figure 2 External Interface Basic Timing
Notes on Data Output Timing (The relationship with the received data)
Figure 3 shows the timing relationship between the received data and the interrupt control signal INT. However, the
delay component relative to the actually received signal due to the demodulation operations in the MSK demodulation
block is ignored. Block synchronization is established by recognizing the BIC code. As shown in figure 3, the data for the
nth packet can be output during the reception of the next packet, packet number n + 1.
Figure 4 shows the output timing for the post-vertical correction data. Vertical correction is executed when the data for a
whole frame is stored in memory, frame synchronization is established, and furthermore horizontal correction was not
able to correct all the packet data. The timing for the start of vertical correction execution is the head of the frame. During
reception of packets 1 to 28 in the nth frame, horizontal correction is performed on each packet, data is passed to the
CPU, and the remaining unused processing time during that interval is used to apply vertical correction to the data from
the previous frame (frame n – 1). The post-vertical correction data (190 blocks of data) is output in order starting when
the 29th packet (block) is received at the rate of one block of output data for every block received. Of the data in the FM
multiplex broadcast frame structure, only the data in the data blocks is output, and the 190th block (the last data block) is
output while the 218th block is being received. As discussed previously (page 11), of the post-vertical correction output
data, the packet data for which horizontal correction completed fully is not output (the INT signal is not issued).
However, it is not the case that the vertical output is speeded up by the amount of the packet data that is not output. For
example, if data packets 1 to 100 were fully corrected in horizontal correction, the point that the 101st post-vertical
correction packet data is output will not be the reception position block number 29 in figure 4, but the reception position
of packet data number 129.
No. 5876-11/16

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