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PDF LC72700 Data sheet ( Hoja de datos )

Número de pieza LC72700
Descripción Mobile FM Multiplex Broadcast Receiver LSI
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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No Preview Available ! LC72700 Hoja de datos, Descripción, Manual

Ordering number : EN4870E
CMOS LSI
LC72700E, LC72700G
Mobile FM Multiplex Broadcast Receiver LSI
Overview
The LC72700E and LC72700G are data decoder LSIs for
receiving DARCTM mobile FM multiplex broadcasts. A
multi-function, compact, adjustment-free system can be
implemented in two chips by combining this LSI with the
LV3400M band-pass filter IC, which extracts the
multiplex components from a composite FM signal.
Functions and Features
• Delay detection scheme using a 1T delay
• Built-in error correction function using a 2T delay
• Digital PLL clock regeneration
• Block and frame synchronization detection with a
settable synchronization protection count
• Settable block identifier code (BIC) detection precision
• Error correction using (272,190) codes
• Built-in frame memory for product codes
• Support for both serial and parallel data I/O
• Package
LC72700E: QFP48E
LC72700G: QFP48G
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Package Dimensions
unit: mm
3156-QFP48E
[LC72700E]
unit: mm
3229-QFP48G
[LC72700G]
SANYO: QFP48E
SANYO: QFP48G
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
VIN1
VIN2
VOUT1
VOUT2
IOUT
Pd max
Topr
Tstg
Conditions
VDD
CL, CE, and DI pins
Input pins other than VIN1
DO pin
Output pins other than VOUT1
BCLOCK, FCLOCK, and DO pins
Ta 85°C
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to VDD + 0.3
–0.3 to +7.0
–0.3 to VDD + 0.3
0 to 4.0
400
–40 to +85
–55 to +125
Unit
V
V
V
V
V
mA
mW
°C
°C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
63097HA (OT)/D3095HA (OT)/D1594TH (OT) No.4870-1/14

1 page




LC72700 pdf
LC72700E, LC72700G
Serial Data I/O Scheme
1. CCB Format
The figure shows the Sanyo audio LSI serial bus format. Data is input and output over a CCB (computer control
bus). This LSI uses an 8-bit address CCB format.
I/O mode
Address
B0 B1 B2 B3 A0 A1 A2 A3
Function
Input
0 1 0 1 1 1 1 1 16-bit control data input
Output
1 1 0 1 1 1 1 1 Data output
I/O mode is set.
2. Serial Data Input Timing
Internal data
3. Serial Data Output Timing
Note: * The DO pin is normally open.
Since the DO pin is an n-channel open-drain output, the time for the data value to change from the low level to the high level depends on the value
of the pull-up resistor used.
No. 4870-5/14

5 Page





LC72700 arduino
LC72700E, LC72700G
Interface: Basic Control Items
To reduce internal memory requirements this LSI limits the data buffer (RAM) area to the minimum required. Since data
received by the LSI is written to the buffer with no gaps, post-correction data that should be read may be overwritten by
new data if there are any delays in data readout.
The output timings for vertically and horizontally corrected data for this LSI are stipulated as follows.
1. When the output data is ready, the LSI sets the DO pin low and drops the INT-R pin to low.
2. In data output, there are periods during which only horizontal data can be read out and periods during which
horizontal and vertical data can be read out time-division multiplexed.
3. The data transfer must be completed within 9 ms after the DO pin goes low. When only horizontal data is output,
data can be transferred during a period of about 18 ms.
Even if the controlling CPU is still reading out data, the data in the output buffer can be overwritten by the next data
after the stipulated period has elapsed.
4. The amount of data that can be read in a single transfer request (INT-R) for both vertical and horizontal data is
limited to only one block of data.
In principle, vertical data is read out in order starting with block number 1 after vertical correction has completed.
Note that the parity block data is not output.
INT-R
DO pin when only
horizontal data is output
DO pin when both
horizontal and vertical
data are output
Horizontal data output period
(horizontal data)
Data not guaranteed
period
(horizontal data)
Horizontal data output period Vertical data output period
Figure 1 External Interface Basic Timing
Data Output Timing (as related to reception data)
Figure 2 shows the timing relationships between the reception data block start signal (BL-CK: pin 23) and the interrupt
control signal (INT-R: pin 25). However, this figure ignores the delay component with respect to the actual received
signal due to the demodulation operation in MSK demodulation blocks. Block synchronization is established by
recognizing BIC codes. As shown in Figure 2, the data from the nth packet (block) is available for output during
reception of the next packet, i.e. packet n+1. When using this LSI, be sure to keep in mind the fact that the block start
signal (BL-CK) output by the LSI is output after the BIC code in the actual reception data has been received.
Figure 3 shows the output timing for vertically corrected data. Vertical correction is used when a complete frame of data
is stored in memory, frame synchronization is established, and all the data packets could not be corrected by horizontal
correction. The frame start defines the timing for the start of vertical correction execution. Horizontal correction is
performed for each packet during reception of packets (blocks) 1 to 28 in the nth frame, and data is passed to the CPU
interface. Vertical correction is performed for the previous frame (frame n-1) data during the idle periods in the reception
process. (However, note that frame and block synchronization must not be lost.)
Vertically corrected data is output at the rate of one block for every block received in order starting with the 29th packet
(block). A total of 190 blocks of data are output. Of the data in the FM multiplex broadcast data structure, only the data
blocks are output, and the last block, the 190th block is output while the 218th block is being received.
No. 4870-11/14

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