|
|
PDF LC72349G Data sheet ( Hoja de datos )
| Número de pieza | LC72349G | |
| Descripción | Low-Voltage ETR Controller with On-Chip LCD Driver | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LC72349G (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
Ordering number : ENN6472
CMOS IC
LC72348G/W, 72349G/W
Low-Voltage ETR Controller
with On-Chip LCD Driver
Overview
The LC72348G/W and LC72349G/W are low-voltage
electronic tuning microcontrollers that include a PLL that
operates up to 230 MHz and a 1/4 duty 1/2 bias LCD
driver on chip. These ICs can contribute to further end
product cost reduction than the LC72341 series while
providing improved standby current characteristics. Also
these ICs can use the application program for the
LC72341 series except the IF counter function.
These ICs are optimal for use in low-voltage portable
audio equipment that includes a radio receiver.
Package Dimensions
unit: mm
3231-QIP64G
[LC72348G, 72349G]
1.0
48
17.2
14.0
0.8 0.35
1.6
1.0
33
32
49
0.15
Function
• Program memory (ROM):
— 3072 × 16 bits (6K bytes)
— 4096 × 16 bits (8K bytes)
LC72348G/W
LC72349 G/W
• Data memory (RAM):
— 192 × 4 bits LC72348 G/W
— 256 × 4 bits LC72349 G/W
• Cycle time: 40 µs (all 1-word instructions) at 75kHz
crystal oscillation
• Stack: 8 levels
• LCD driver: 48 to 80 segments (1/4 duty, 1/2 bias drive)
• Interrupts: One external interrupt
Timer interrupts (1, 5, 10, and 50 ms)
• A/D converter: Three input channels
(5-bit successive approximation
conversion)
• Input ports: 7 ports (of which three can be switched for
use as A/D converter inputs)
• Output ports: 6 ports (of which 1 can be switched for use
as the beep tone output and 2 are open-
drain ports)
• I/O ports: 16 ports (of which 8 can be switched for use
as LCD ports and as mask options)
Continued on next page.
64
1
17
16
0.1
2.15
unit: mm
3190-SQFP64
15.6
0.8
SANYO: QFP64G
[LC72348W, 72349W]
12.0
10.0
1.25
0.5 0.18
1.25
48
49
33
32
0.15
64
1
17
16
0.5 0.5 SANYO: SQFP64
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
32700RM (OT) No. 6472-1/14
1 page  
LC72348G/W, 72349G/W
Note: * C(1), C(2), and C(3) must be connected even if an LCD is not used.
0.1 to 1 µF
C(C1)
0.1 to 1 µF
0.1 to 1 µF
C(C2)
C(C3)
DBR1
DBR2
DBR3
DBR4
Notes: *1. The capacitors C(1), C(2), and C(3) must be connected to the DBR pins.
*2. VSENSE
When the VDD voltage drops, the VSENSE flag is set when that voltage is 1.75 V (typical). Applications can
check the VSENSE flag using the TST instruction. Battery or other power source depletion can be easily
measured by monitoring this flag.
Note that the voltage for VSENSE detection differs for the falling and rising directions. Thus, after the VSENSE
flag has been set due to a voltage drop, it will not be reset if the voltage rises by under 0.1 V.
VDD
VDD
1.9 V
1.6 V
RESET←
→ SET
VSENSE (1)
For a falling voltage
t
*3. Halt mode current measurement circuit
2.1 V
1.7 V
SET←
→RESET
VSENSE (2)
For a rising voltage
t
*4. Backup mode current measurement circuit
7 pF
A
75 kHz
XOUT VDD RESDBR1
XIN
7pF
DBR2
DBR3
FMIN
AMIN
TEST1, 2
DBR4
VSS
PA, PF
AGND
AIN
0.1 µF
0.1 µF
0.1 µF
7 pF
A
75 kHz
XOUT VDD RESDBR1
XIN
7pF
DBR2
DBR3
FMIN
AMIN
TEST1, 2
DBR4
VSS
AGND
AIN
0.1 µF
0.1 µF
0.1 µF
With all ports other than those specified above left open.
With output mode selected for PC and PD.
With segments S13 to S20 selected.
With all ports other than those specified above left open.
With output mode selected for PC and PD.
With segments S13 to S20 selected.
No. 6472-5/14
5 Page 
LC72348G/W, 72349G/W
LC72340 Series Instruction Set
Terminology
ADDR
: Program memory address
b : Borrow
C : Carry
DH : Data memory address High (Row address) [2 bits]
DL : Data memory address Low (Column address) [4 bits]
I : Immediate data [4 bits]
M : Data memory address
N : Bit position [4 bits]
Rn : Resister number [4 bits]
Pn : Port number [4 bits]
PW : Port control word number [4 bits]
r : General register (One of the addresses from 00H to 0FH of BANK0)
( ), [ ]
: Contents of register or memory
M (DH, DL) : Data memory specified by DH, DL
Instruc-
tions
Mnemonic
AD
ADS
AC
ACS
AI
AIS
AIC
AICS
SU
SUS
SB
SBS
SI
SIS
SIB
SIBS
Operand
1st 2nd
rM
rM
rM
rM
MI
MI
MI
MI
rM
rM
rM
rM
MI
MI
MI
MI
Function
Add M to r
Add M to r, then skip if carry
Add M to r with carry
Add M to r with carry,
then skip if carry
Add I to M
Add I to M, then skip if carry
Add I to M with carry
Add I to M with carry,
then skip if carry
Subtract M from r
Subtract M from r,
then skip if borrow
Subtract M from r with borrow
Subtract M from r with borrow,
then skip if borrow
Subtract I from M
Subtract I from M,
then skip if borrow
Subtract I from M with borrow
Subtract I from M with borrow,
then skip if borrow
Operations function
Instruction format
f edcba9876543210
r ← (r) + (M)
0 1 0 0 0 0 DH
DL
r
r ← (r) + (M), skip if carry 0 1 0 0 0 1 DH
DL
r
r ← (r) + (M) + C
0 1 0 0 1 0 DH
DL
r
r ← (r) + (M) + C
skip if carry
0 1 0 0 1 1 DH
DL
r
M ← (M) + I
0 1 0 1 0 0 DH
DL
I
M ← (M) + I, skip if carry 0 1 0 1 0 1 DH
DL
I
M ← (M) + I + C
0 1 0 1 1 0 DH
DL
I
M ← (M) + I + C,
skip if carry
0 1 0 1 1 1 DH
DL
I
r ← (r) – (M)
0 1 1 0 0 0 DH
DL
r
r ← (r) – (M),
skip if borrow
0 1 1 0 0 1 DH
DL
r
r ← (r) – (M) – b
0 1 1 0 1 0 DH
DL
r
r ← (r) – (M) – b,
skip if borrow
0 1 1 0 1 1 DH
DL
r
M ← (M) – I
0 1 1 1 0 0 DH
DL
I
M ← (M) – I,
skip if borrow
0 1 1 1 0 1 DH
DL
I
M ← (M) – I – b
0 1 1 1 1 0 DH
DL
I
M ← (M) – I – b,
skip if borrow
0 1 1 1 1 1 DH
DL
I
Continued on next page.
No. 6472-11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LC72349G.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LC72349 | Low-Voltage ETR Controller with On-Chip LCD Driver | Sanyo Semicon Device |
| LC72349G | Low-Voltage ETR Controller with On-Chip LCD Driver | Sanyo Semicon Device |
| LC72349W | Low-Voltage ETR Controller with On-Chip LCD Driver | Sanyo Semicon Device |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |