PDF PCF2123 Data sheet ( Hoja de datos )

Número de pieza	PCF2123
Descripción	SPI Real time clock/calendar
Fabricantes	NXP Semiconductors
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No Preview Available ! PCF2123 SPI Real time clock/calendar Rev. 01 — 19 November 2008 www.DataSheet4U.com Product data sheet 1. General description The PCF2123 is a CMOS real time clock and calendar optimized for low power applications. Data is transferred serially via a Serial Peripheral Interface bus (SPI-bus) with a maximum data rate of 6.25 Mbit/s. An alarm and timer function is also available providing the possibility to generate a wake-up signal on an interrupt pin. An offset register allows ﬁne tuning of the clock. 2. Features I Real time clock provides year, month, day, weekday, hours, minutes and seconds based on a 32.768 kHz quartz crystal I Low backup current while running: typical 100 nA at VDD = 2.0 V and Tamb = 25 °C I Resolution: seconds to years I Watchdog functionality I Freely programmable timer and alarm with interrupt capability I Clock operating voltage: 1.1 V to 5.5 V I 3 line SPI-bus with separate combinable data input and output I Serial interface at VDD = 1.6 V to 5.5 V I 1 second or 1 minute interrupt output I Integrated oscillator load capacitors for CL = 7 pF I Internal power-on reset I Open-drain interrupt and clock output pins I Programmable offset register for frequency adjustment 3. Applications I Time keeping application I Battery powered devices I Metering I High duration timers I Daily alarms I Low standby power applications 1 page NXP Semiconductors PCF2123 SPI Reawl wtiwm.DeactaloSchkee/ct4aUle.cnodmar 7.2 Pin description Table 3. Symbol OSCI Pin description Pin TSSOP14 1 HVQFN16 16 OSCO 2 1 n.c. 3, 11 6, 7, 14, 15 TEST 4 2 INT CE VSS SDO 5 6 7 8 3 4 5[1] 8 SDI SCL CLKOE CLKOUT VDD 9 10 12 13 14 9 10 11 12 13 Description PCF2123U/10 7 oscillator input; high-impedance node; minimize wire length between quartz and package 8 oscillator output; high-impedance node; minimize wire length between quartz and package - do not connect and do not use as feed through; connect to VDD if ﬂoating pins are not allowed 9 test pin; not user accessible; connect to VSS or leave ﬂoating (internally pulled down) 10 interrupt output (open-drain; active LOW) 11 chip enable input (active HIGH) with internal pull down 12[2] ground 1 serial data output, push-pull; high-impedance when not driving; can be connected to SDI for single wire data line 2 serial data input; may ﬂoat when CE is inactive 3 serial clock input; may ﬂoat when CE is inactive 4 CLKOUT enable or disable pin; enable is active HIGH 5 clock output (open-drain) 6 supply voltage; positive or negative steps in VDD may affect oscillator performance; recommend 10 nF decoupling close to device (see Figure 28) [1] The die paddle (exposed pad) is wired to VSS but should not be electrically connected. [2] The substrate (rear side of the die) is wired to VSS but should not be electrically connected. 8. Device protection diagram PCF2123 VDD OSCI OSCO TEST INT CE VSS CLKOE CLKOUT SCL SDI SDO 001aai552 Fig 5. Device diode protection diagram of PCF2123 PCF2123_1 Product data sheet Rev. 01 — 19 November 2008 © NXP B.V. 2008. All rights reserved. 5 of 54 5 Page NXP Semiconductors PCF2123 SPI Reawl wtiwm.DeactaloSchkee/ct4aUle.cnodmar 9.3.2 Register Control_2 Table 6. Register Control_2 (address 01h) bits description Bit Symbol Value Description Reference 7 MI 0 minute interrupt is disabled Section 9.8.1 1 minute interrupt is enabled 6 SI 0 second interrupt is disabled 1 second interrupt is enabled 5 MSF 0 no minute or second interrupt generated 1 ﬂag set when minute or second interrupt generated; ﬂag must be cleared to clear interrupt when TI_IP = 0 4 TI_TP 0 interrupt pin follows timer ﬂags Section 9.9.2 1 interrupt pin generates a pulse 3 AF 0 no alarm interrupt generated Section 9.7.1 1 ﬂag set when alarm triggered; ﬂag must be cleared to clear interrupt 2 TF 0 no countdown timer interrupt generated - 1 ﬂag set when countdown timer interrupt generated; ﬂag must be cleared to clear interrupt when TI_IP = 0 1 AIE 0 no interrupt generated from the alarm ﬂag Section 9.9.3 1 interrupt generated when alarm ﬂag set 0 TIE 0 no interrupt generated from the countdown Section 9.9.2 timer 1 interrupt generated by the countdown timer 9.4 OS ﬂag The PCF2123 includes a ﬂag (bit OS) which is set whenever the oscillator is stopped (see Figure 8 and Figure 9). The ﬂag will remain set until cleared by software. If the ﬂag cannot be cleared, then the PCF2123 oscillator is not running. This method can be used to monitor the oscillator and to determine if the supply voltage has reduced to the point where oscillation fails. VDD battery operation main supply VOSC(MIN) PCF2123_1 Product data sheet Fig 8. OS set by failing VDD Rev. 01 — 19 November 2008 t 001aai561 © NXP B.V. 2008. All rights reserved. 11 of 54 11 Page

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