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PDF FDMS7600AS Data sheet ( Hoja de datos )

Número de pieza FDMS7600AS
Descripción Dual N-Channel PowerTrench MOSFET
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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FDMS7600AS
Dual N-Channel PowerTrench® MOSFET
N-Channel: 30 V, 30 A, 7.5 mN-Channel: 30 V, 40 A, 2.8 m
December 2009
Features
General Description
Q1: N-Channel
„ Max rDS(on) = 7.5 mat VGS = 10 V, ID = 12 A
„ Max rDS(on) = 12 mat VGS = 4.5 V, ID = 10 A
Q2: N-Channel
„ Max rDS(on) = 2.8 mat VGS = 10 V, ID = 20 A
„ Max rDS(on) = 3.3 mat VGS = 4.5 V, ID = 18 A
„ RoHS Compliant
This device includes two specialized N-Channel MOSFETs in a
dual MLP package.The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Applications
„ Computing
„ Communications
„ General Purpose Point of Load
„ Notebook VCORE
S2
S2 S2
G2
S1/D2
D1
S2 5
S2 6
Q2
4 D1
3 D1
D1
D1
D1 G1
Top Bottom
Power 56
S2 7
G2 8
2 D1
Q1 1 G1
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
PD
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
Power Dissipation for Single Operation
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 3)
TC = 25 °C
TC = 25 °C
TA = 25 °C
TA = 25 °C
TA = 25 °C
Q1 Q2
30 30
±20 ±20
30 40
50
121a
120
221b
40
2.21a
1.01c
60
2.51b
1.01d
-55 to +150
Units
V
V
A
W
°C
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
571a
1251c
3.5
501b
1201d
2
°C/W
Device Marking
FDMS7600AS
Device
FDMS7600AS
Package
Power 56
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
©2009 Fairchild Semiconductor Corporation
FDMS7600AS Rev.C
1
www.fairchildsemi.com

1 page




FDMS7600AS pdf
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
www.DataSheet4U.com
10
ID = 12 A
8
6
4
2
VDD = 10 V
VDD = 15 V
VDD = 20 V
0
0 5 10 15 20
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
2000
1000
Ciss
Coss
100
f = 1 MHz
Crss
VGS = 0 V
10
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure8. Capacitance vsDrain
to Source Voltage
60
VGS = 10 V
40
VGS = 4.5 V
20 Limited by Package
RθJC = 3.5 oC/W
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
Figure 9. Maximum Continuous Drain Current vs
Case Temperature
1000
100
100
100us
10
1 ms
1
THIS AREA IS
LIMITED BY rDS(on)
10 ms
100 ms
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 125 oC/W
TA = 25 oC
0.01
0.01 0.1
1
1s
10s
DC
10 100 200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 10. Forward Bias Safe Operating Area
SINGLE PULSE
RθJA = 125 oC/W
TA = 25 oC
10
1
0.5
10-4
10-3
10-2
10-1
1
t, PULSE WIDTH (s)
10
Figure 11. Single Pulse Maximum Power Dissipation
©2009 Fairchild Semiconductor Corporation
FDMS7600AS Rev.C
5
100 1000
www.fairchildsemi.com

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FDMS7600AS arduino
Dimensional Outline and Pad Layout
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©2009 Fairchild Semiconductor Corporation
FDMS7600AS Rev.C
11
www.fairchildsemi.com

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