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PDF MAX1169 Data sheet ( Hoja de datos )
| Número de pieza | MAX1169 | |
| Descripción | 2-Wire Serial ADC | |
| Fabricantes | Maxim Integrated Products | |
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19-2654; Rev 2; 12/10
EVAALVUAAILTAIOBNLEKIT
58.6ksps, 16-Bit,
2-Wire Serial ADC in a 14-Pin TSSOP
General Description
The MAX1169 is a low-power, 16-bit successive-
approximation analog-to-digital converter (ADC). The
device features automatic power-down, an on-chip
4MHz clock, a +4.096V internal reference, and an
I2C-compatible 2-wire serial interface capable of both
fast and high-speed modes.
The MAX1169 operates from a single supply and con-
sumes 5mW at the maximum conversion rate of
58.6ksps. AutoShutdown™ powers down the device
between conversions, reducing supply current to less
than 50µA at a 1ksps throughput rate. The option of a
separate digital supply voltage allows direct interfacing
with +2.7V to +5.5V digital logic.
The MAX1169 performs a unipolar conversion on its
single analog input using its internal 4MHz clock. The
full-scale analog input range is determined by the inter-
nal reference or by an externally applied reference volt-
age ranging from 1V to VAVDD.
The four address select inputs (ADD0 to ADD3) allow
up to 16 MAX1169 devices on the same bus.
The MAX1169 is packaged in a 14-pin TSSOP and
operates over an extended temperature range. Refer to
the MAX1069 data sheet for a 14-bit device in a pin-
compatible package.
Applications
Hand-Held Portable Applications
Medical Instruments
Battery-Powered Test Equipment
Solar-Powered Remote Systems
Received-Signal-Strength Indicators
System Supervision
Features
o High-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
o +4.75V to +5.25V Single Supply
o +2.7V to +5.5V Adjustable Logic Level
o Internal +4.096V Reference
o External Reference: 1V to VAVDD
o Internal 4MHz Conversion Clock
o 58.6ksps Sampling Rate
o AutoShutdown Between Conversions
o Low Power
5.0mW at 58.6ksps
4.2mW at 50ksps
2.0mW at 10ksps
0.23mW at 1ksps
3µW in Shutdown
o Small 14-Pin TSSOP Package
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
MAX1169BEUD+ -40°C to +85°C 14 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
INL
(LSB)
±2
Pin Configuration
TOP VIEW
DGND 1
SCL 2
SDA 3
ADD2 4
ADD1 5
ADD0 6
DVDD 7
MAX1169
14 ADD3
13 REF
12 REFADJ
11 AGNDS
10 AIN
9 AGND
8 AVDD
TSSOP
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external
reference applied to REF, REFADJ = AVDD, CREF = 10μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figure 1b and Figure 2)
Serial Clock Frequency
fSCLH (Note 11)
Hold Time (Repeated) Start
Condition
tHD, STA
Low Period of the SCL Clock
High Period of the SCL Clock
tLOW
tHIGH
Setup Time for a Repeated
START Condition
tSU, STA
MIN TYP MAX UNITS
1.7 MHz
160 ns
320 ns
120 ns
160 ns
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
tHD, DAT
tSU, DAT
(Note 9)
tRCL (Note 10)
0 150 ns
10 ns
10 80 ns
Rise Time of SCL Signal After
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
Capacitive Load for Each Bus
Pulse Width of Spike Suppressed
tRCL1
tFCL
tRDA
tFDA
tSU, STO
CB
tSP
(Note 10)
(Note 10)
(Note 10)
(Note 10)
20 160 ns
20 80 ns
20 160 ns
20 160 ns
160 ns
400 pF
10 ns
Note 1:
Note 2:
Note 3:
Note 4:
DC accuracy is tested at VAVDD = +5.0V and VDVDD = +3.0V. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection test.
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Offset nullified.
One sample is achieved every 18 clocks in continuous conversion mode:
fSAMPLE
=
⎛ 18 clocks
⎝⎜ fSCL
⎞ -1
+ t CONV ⎠⎟
Note 5: The track/hold acquisition time is two SCL cycles as illustrated in Figure 11:
t ACQ
=
2
×
⎛
⎝⎜
1
fSCL
⎞
⎠⎟
Note 6:
Note 7:
Note 8:
A filter on SDA and SCL delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and
50ns in fast mode.
ADC performance is limited by the converter’s noise floor, typically 225μVP-P.
PSRR =
⎡⎣ VFS (5.25V)-VFS (4.75V) ⎤⎦
×
2N
VREF
where N is the number of bits (16).
5.25V - 4.75V
_______________________________________________________________________________________ 5
5 Page 
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
Pin Description
PIN NAME
FUNCTION
1 DGND Digital Ground
2 SCL Clock Input
3
SDA
Data Input/Output
4
ADD2
Address Select Input 2
5
ADD1
Address Select Input 1
6
ADD0
Address Select Input 0
7 DVDD Digital Power Input. Bypass to DGND with a 0.1μF capacitor.
8
AVDD
Analog Power Input. Bypass to AGND with a 0.1μF capacitor.
9 AGND Analog Ground
10 AIN Analog Input
11 AGNDS Analog Signal Ground. Negative reference for analog input. Connect to AGND.
12 REFADJ Internal Reference Output and Reference Buffer Input. Bypass to AGND with a 0.1μF capacitor.
Connect REFADJ to AVDD to disable the internal bandgap reference and reference-buffer amplifier.
13 REF Reference Buffer Output and External Reference Input. Bypass to AGND with a 10μF capacitor
when using the internal reference.
14
ADD3
Address Select Input 3
Detailed Description
The MAX1169 ADC uses successive-approximation
conversion (SAR) techniques and on-chip track-and-
hold (T/H) circuitry to capture and convert an analog
signal to a serial 16-bit digital output.
The MAX1169 performs a unipolar conversion on its
single analog input using its internal 4MHz clock. The
full-scale analog input range is determined by the inter-
nal reference or by an externally applied reference volt-
age ranging from 1V to VAVDD.
The flexible 2-wire serial interface provides easy con-
nection to microcontrollers (μCs) and supports data
rates up to 1.7MHz. Figure 3 shows the simplified func-
tional diagram for the MAX1169 and Figure 4 shows the
typical application circuit.
Power Supply
To maintain a low-noise environment, the MAX1169
provides separate analog and digital power-supply
inputs. The analog circuitry requires a +5V supply and
consumes only 900μA at sampling rates up to
58.6ksps. The digital supply voltage accepts voltages
from +2.7V to +5.5V to ensure compatibility with low-
voltage ASICs. The MAX1169 wakes up in shutdown
mode when power is applied irrespective of the AVDD
and DVDD sequence.
Analog Input and Track/Hold
The MAX1169 analog input contains a T/H capacitor,
T/H switches, comparator, and a switched capacitor
digital-to-analog converter (DAC) (Figure 5).
As shown in Figure 11c, the MAX1169 acquisition peri-
od is the two clock cycles prior to the conversion peri-
od. The T/H switches are normally in the hold position.
During the acquisition period, the T/H switches are in
the track position and CT/H charges to the analog input
signal. Before a conversion begins, the T/H switches
move to the hold position retaining the charge on CT/H
as a sample of the analog input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 16-bit resolution. This is equiva-
lent to transferring a charge of 35pF × (VAIN - VAGNDS)
from CT/H to the binary weighted capacitive DAC,
forming a digital representation of the analog input sig-
nal. During the conversion period, the MAX1169 holds
SCL low (clock stretching).
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX1169.PDF ] | |
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