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PDF LC72122V Data sheet ( Hoja de datos )

Número de pieza LC72122V
Descripción PLL Frequency Synthesizer for Portable Equipment Electronic Tuning
Fabricantes Sanyo Semicon Device 
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No Preview Available ! LC72122V Hoja de datos, Descripción, Manual

Ordering number : ENN6113A
CMOS IC
LC72122V
PLL Frequency Synthesizer
for Portable Equipment Electronic Tuning
Overview
The LC72122V is a low-voltage (1.8 to 3.6 V) PLL
frequency synthesizer IC that allows portable TV
(VHF)/FM/AM tuners to be constructed easily.
Features
• High-speed programmable frequency divider
— FMIN: 10 to 250 MHz ..Pulse swallower
(divide-by-two prescaler built in)
— AMIN: 2 to 40 MHz ......Pulse swallower
0.5 to 10 MHz ...Direct division
• IF counter
— IFIN: 0.4 to 12 MHz ......For use as an AM/FM IF
counter
• Reference frequency
— Selectable from one of nine frequencies (crystal
oscillator: 75 kHz)
1, 2.5, 3, 5, 3.125, 6.25, 12.5, 15, and 25 kHz
• Phase comparator
— Supports dead zone control
— Built-in unlock detection circuit
— Built-in deadlock clear circuit
— Sub-charge pump for fast frequency locking
• Built-in MOS transistor for forming an active low-pass
filter
• I/O ports
— Dedicated output ports: 3
— I/O ports: 2
— Supports clock time base output
• Serial Data I/O
— Supports CCB format communication with the
system controller.
• Operating ranges
— Supply voltage: 1.8 to 3.6 V
— Operating temperature: –20 to +70°C
• Package
—SSOP20
Package Dimensions
unit: mm
3179A-SSOP20
[LC72122V]
20 11
1 10
6.7
0.15
0.22 0.65 0.43
SANYO: SSOP20
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D0199TH (OT) /O3099TH (OT) /D2598RM (OT) No. 6113-1/22

1 page




LC72122V pdf
Pin Descriptions
Symbol
Pin No.
Type
LC72122V
Functions
XIN
XOUT
19
Xtal
20
• Crystal oscillator connections (75 kHz)
Circuit configuration
FMIN
• FMIN is selected when the serial data input DVS bit is
set to 1.
• The input frequency range is from 10 to 250 MHz.
12
Local oscillator
signal input
• The input signal passes through the internal divide-by-
two prescaler and is input to the swallow counter.
• The divisor can be in the range 272 to 65535. However,
since the signal has passed through the divide-by-two
prescaler, the actual divisor is twice the set value.
AMIN
• AMIN is selected when the serial data input DVS bit is
set to 0.
• When the serial data input SNS bit is set to 1:
— The input frequency range is 2 to 40 MHz.
— The signal is directly input to the swallow counter.
11
Local oscillator
signal input
— The divisor can be in the range 272 to 65535, and
the divisor used will be the value set.
• When the serial data input SNS bit is set to 0:
— The input frequency range is 0.5 to 10 MHz.
— The signal is directly input to a 12-bit programmable
divider.
— The divisor can be in the range 4 to 4095, and the
divisor used will be the value set.
CE
DI
CL
DO
VDD
VSSd
• Set this pin high when inputting (DI) or outputting (DO)
serial data.
1
Chip enable
• Up to 6.5 V may be applied, regardless of the actual
supply voltage (VDD).
2 Input data
• Inputs serial data transferred from the controller to the
LC72122V.
• Up to 6.5 V may be applied, regardless of the actual
supply voltage (VDD).
3 Clock
• Used as the synchronization clock when inputting (DI) or
outputting (DO) serial data.
• Up to 6.5 V may be applied, regardless of the actual
supply voltage (VDD).
• Outputs serial data transferred from the LC72122V to
4 Output data
the controller. The data output is determined by the
DOC0 to DOC2 bits in the serial data.
• The LC72122V power supply pin. (VDD = 1.8 to 3.6 V)
13
Power supply
• The power on reset circuit operates when power is first
applied.
14 Ground
• The LC72122V ground
Continued on next page.
No. 6113-5/22

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LC72122V arduino
LC72122V
Continued from preceding page.
No. Control block/data
IF counter control data
(11) IFS
Sub-charge pump control
(12) data
SUBC
IC test data
TEST 0 to TEST2
(13)
(14) DNC
Description
• IFIN pin input sensitivity control data. This data should be set to 1 in normal operation.
Setting this data to 0 switches the LC72122V to a reduced input sensitivity mode in which
the sensitivity is reduced by 10 to 30 mVrms.
• This data controls the sub-charge pump (PDS) which is provided for fast locking.
By setting SUBC to 1, applications can set the sub-charge pump circuit to the operating
state and increase the speed of frequency looking.
• IC test data
TEST0
TEST1 All three bits must be set to 0.
TEST2
All the test data is set to 0 at a power-on reset.**
Data is set to 0
Related data
UL0, UL1
**Note : Although the IC is initialized after power is first applied by the power on reset circuit, applications must also send a full set of data over the CCB bus
immediately after power is first applied to assure safe and stable operation.
DO Output Data (Serial Data Output) Structure
3. OUT mode
*
Note: * Data with a value of “0”
DO Output Data
No. Control block/data
I/O port data
I2, I1
(1)
PLL unlock data
(2) UL
IF counter binary data
(3) C19 to C0
Description
• Data latched from the states of the I/O ports, pins IO1 and IO2.
• This data reflects the pin states, regardless of whether they are in input or output mode.
• The data is latched when OUT mode is selected.
I1 IO1 pin state High: 1
I2 IO2 pin state Low: 0
• Data latched from the state of the unlock detection circuit
UL 0: Unlocked
UL 1: Locked or in detection stopped mode
• Data latched from the state of the IF counter, which is a 20-bit binary counter.
C19 Binary counter MSB
C0 Binary counter LSB
Related data
IOC1,
IOC2
UL0,
UL1
CTE,
GT0,
GT1
No. 6113-11/22

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