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PDF LC72121 Data sheet ( Hoja de datos )

Número de pieza LC72121
Descripción PLL Frequency Synthesizers for Electronic Tuning
Fabricantes Sanyo Semicon Device 
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No Preview Available ! LC72121 Hoja de datos, Descripción, Manual

Ordering number : EN*5815A
CMOS IC
LC72121, 72121M, 72121V
PLL Frequency Synthesizers for Electronic Tuning
Preliminary
Overview
The LC72121 and the LC72121M and the LC72121V are
high input sensitivity (20 mVrms at 130 MHz) PLL
frequency synthesizers for 3 V systems. These ICs are
serial data (CCB) compatible with the LC72131, and
feature the improved input sensitivity and lower spurious
radiation (provided by a redesigned ground system)
required in high-performance AM/FM tuners.
Functions
• High-speed programmable divider
— FMIN: 10 to 160 MHz ... Pulse swallower technique
(With built-in divide-by-2
prescaler)
— AMIN: 2 to 40 MHz ... Pulse swallower technique
0.5 to 10 MHz ... Direct division technique
• IF counter
— IFIN: 0.4 to 12 MHz ... For AM and FM IF counting
• Reference frequency
— One of 12 reference frequencies can be selected
(using a 4.5 or 7.2 MHz crystal element)
1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50, or 100
kHz
• Phase comparator
— Supports dead zone control.
— Built-in unlocked state detection circuit
— Built-in deadlock clear circuit
• An MOS transistor for an active low-pass filter is built
in.
• I/O ports
— Output-only ports: 4 pins
— I/O ports: 2 pins
— Supports the output of a clock time base signal.
• Operating ranges
— Supply voltage: 2.7 to 3.6 V
— Operating temperature: – 40 to 85°C
• Package
— DIP22S, MFP24S, SSOP24
• Comparison with the LC72131/M
— Serial data compatible (CCB)
— Identical pin functions
— Two VSS pins were added.
— The DIP version is pin compatible (VSS pins were
inserted as the DIP22S NC pins.)
— The MFP product provides a modified pin
assignment (The MFP20 package was replaced by
an MFP24 package, and extra VSS pins were added.)
— The SSOP24 is a newly developed package that has
the same pin assignment as the MFP24S product.
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
70398RM (OT) No. 5815-1/22

1 page




LC72121 pdf
LC72121, 72121M, 72121V
Continued from preceding page.
Parameter
Output low-level voltage
Input high-level current
Input low-level current
Output off leakage current
High-level 3-state off leakage current
Low-level 3-state off leakage current
Input capacitance
Supply current
Symbol
Conditions
VOL1
VOL2
VOL3
VOL4
IIH1
IIH2
IIH3
IIH4
IIH5
IIH6
IIL1
IIL2
IIL3
IIL4
IIL5
IIL6
IOFF1
IOFF2
IOFFH
IOFFL
CIN
IDD1
IDD2
IDD3
PD: IO = 1 mA
BO1 to BO4, IO1, IO2: IO = 1 mA
BO1 to BO4, IO1, IO2: IO = 8 mA
DO: IO = 5 mA
AOUT: IO = 1 mA, AIN = 1.3 V
CE, DI, CL: VI = 6.5 V
IO1, IO2: VI = 13 V
XIN: VI = VDD
FMIN, AMIN: VI = VDD
IFIN: VI = VDD
AIN: VI = 6.5 V
CE, DI, CL: VI = 0 V
IO1, IO2: VI = 0 V
XIN: VI = 0 V
FMIN, AMIN: VI = 0 V
IFIN: VI = 0 V
AIN: VI = 0 V
BO1 to BO4, IO1, IO2, AOUT: VO = 13 V
DO: VO = 6.5 V
PD: VO = VDD
PD: VO = 0 V
FMIN
VDD: Xtal = 7.2 MHz, fIN2 = 130 MHz,
VIN2 = 20 mVrms
VDD: PLL block stopped (PLL inhibit mode)
Crystal oscillator operating
(crystal frequency: 7.2 MHz)
VDD: PLL block stopped, crystal oscillator
stopped
Ratings
min typ
1.3
2.5
5.0
1.3
2.5
5.0
0.01
0.01
6
2.5
max
1.0
0.2
1.6
1.0
0.5
5.0
5.0
8
15
30
200
5.0
5.0
8
15
30
200
5.0
5.0
200
200
6
Unit
V
V
V
V
V
µA
µA
µA
µA
µA
nA
µA
µA
µA
µA
µA
nA
µA
µA
nA
nA
pF
mA
0.3 mA
10 µA
Pin Descriptions
Pin
name
Pin No.
LC72121
LC72121M
LC72121V
Type
Function
Equivalent circuit
XIN
XOUT
1
22
1
Xtal
24
• Crystal oscillator element connections (4.5 or 7.2 MHz)
FMIN
16
AMIN
15
• FMIN is selected when DVS in the serial data is set to 1.
• Input frequency: 10 to 160 MHz
Local
• The signal is passed through an internal divide-by-two prescaler and
17 oscillator
then input to the swallow counter.
signal input • The divisor can be set to a value in the range 272 to 65535. Since
the internal divide-by-two prescaler is used, the actual divisor will be
twice the set value.
• AMIN is selected when DVS in the serial data is set to 0.
• When SNS in the serial data is set to 1:
• Input frequency: 2 to 40 MHz
• The signal is input to the swallow counter directly.
Local
• The divisor can be set to a value in the range 272 to 65535. The
16 oscillator
set value becomes the actual divisor.
signal input • When SNS in the serial data is set to 0:
• Input frequency: 0.5 to 10 MHz
• The signal is input to a 12-bit programmable divider directly.
• The divisor can be set to a value in the range 4 to 4095. The set
value becomes the actual divisor.
Continued on next page.
No. 5815-5/22

5 Page





LC72121 arduino
LC72121, 72121M, 72121V
Continued from preceding page.
No. Control block/data
Function
9
Clock time base • Setting the TBC bit to 1 causes an 8-Hz clock time base signal with a 40% duty to be output from the
TBC
BO1 pin. (The BO1 data will be ignored.)
• Forcibly controls the charge pump output.
DLC Charge pump output
Charge pump
10 control data
0 Normal operation
1 Forced to low
DLC
* If the circuit deadlocks due to the VCO control voltage (Vtune) being 0 and the VCO being stopped,
applications can get out of the deadlocked state by setting the charge pump output to low and setting
Vtune to VCC. (Deadlock clear circuit)
IF counter control • This data is normally set to 1. Setting this data to 0 sets the circuit to reduced input sensitivity mode, in
11 data which the sensitivity is reduced by about 10 to 30 mV rms.
IFS * See the “IF Counter Operation” section for details.
• Test data
Test data
12
TEST0 to 2
TEST0
TEST1
TEST2
All these bits must be set to 0.
All these bits are set to 0 after a power on reset.
13
DNC
• This bit must be set to 0.
Related data
BO1
Structure of the DO Output Data (serial data output)
• OUT mode
DO Output Data
No. Control block/data
Function
• Data latched from the I/O port IO pin states.
I/O port data
• These bits reflect the pin states regardless of the I/O port mode (input or output).
1 The data is latched at the point the circuit enters data output mode (OUT mode).
12, I1
I1 The IO1 pin state H : 1
I2 The IO2 pin state L : 0
PLL unlocked state • Indicates the state of the unlocked state detection circuit.
2 data
UL 0: When the PLL is unlocked.
UL UL 1: When the PLL is locked or in the detection disabled mode.
IF counter binary • Indicates the value of the IF counter (20-bit binary counter).
3 data
C19 MSB of the binary counter
C19 to C0
C0 LSB of the binary counter
Related data
IOC1
IOC2
UL0
UL1
CTE
GT0
GT1
No. 5815-11/22

11 Page







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