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PDF TDA8034HN Data sheet ( Hoja de datos )
| Número de pieza | TDA8034HN | |
| Descripción | Smart Card Interface | |
| Fabricantes | NXP Semiconductors | |
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TDA8034HN
Smart card interface
Rev. 01 — 5 February 2010
www.DataSheet4U.com
Product data sheet
1. General description
The TDA8034HN is a cost-effective analog interface for asynchronous and synchronous
smart cards operating at 5 V, 3 V or 1.8 V. Using few external components, the
TDA8034HN provides all supply, protection and control functions between a smart card
and the microcontroller.
2. Features
I Integrated circuit smart card interface in an HVQFN24 package
I 5 V, 3 V or 1.8 V smart card supply
I Very low power consumption in Deep Shutdown mode
I Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8)
I VCC regulation:
N 5 V, 3 V or 1.8 V ± 5 % using two low ESR multilayer ceramic capacitors: one of
220 nF and one of 470 nF
N current spikes of 40 nA/s (VCC = 5 V and 3 V) or 15 nA/s (VCC =1.8 V) up to
20 MHz, with controlled rise and fall times and filtered overload detection of
approximately 120 mA
I Thermal and short-circuit protection for all card contacts
I Automatic activation and deactivation sequences triggered by a short-circuit, card
take-off, overheating, falling VDD, VDD(INTF) or VDDP
I Enhanced card-side ElectroStatic Discharge (ESD) protection of > 6 kV
I External clock input up to 26 MHz connected to pin XTAL1
I Card clock generation up to 20 MHz using pins CLKDIV1 and CLKDIV2 with
synchronous frequency changes of fxtal, 1⁄2 fxtal, 1⁄4 fxtal or 1⁄8 fxtal
I Non-inverted control of pin RST using pin RSTIN
I Compatible with ISO 7816, NDS and EMV 4.2 payment systems
I Supply supervisor for killing spikes during power on and off:
N using a fixed threshold
N using an external resistor bridge with threshold adjustment
I Built-in debouncing on card presence contacts (typically 8 ms)
I Multiplexed status signal using pin OFFN
1 page  
NXP Semiconductors
TDA8034HNwww.DataSheet4U.com
Smart card interface
Table 3. Pin description …continued
Symbol
Pin Supply Type[1] Description
VDDP
16 VDDP
P
low-dropout regulator input supply voltage
VDD
17 VDD
P
digital supply voltage
PORADJ
OFFN
I/OUC
AUX1UC
AUX2UC
XTAL1
18 VDD(INTF) I
19 VDD(INTF) O
20 VDD(INTF) I/O
21 VDD(INTF) I/O
22 VDD(INTF) I/O
23 VDD
I
power-on reset threshold adjustment input using an optional external resistor bridge
NMOS interrupt to microcontroller[4]; active LOW; see Section 8.10 on page 11
microcontroller input/output data line[3]
auxiliary microcontroller input/output data line[3]
auxiliary microcontroller input/output data line[3]
crystal connection input
XTAL2
24 VDD
O
crystal connection output
[1] I = input, O = output, I/O = input/output, G = ground and P = power supply.
[2] If pin PRESN is HIGH, the card is considered to be present. During card insertion, debouncing can occur on these signals. To counter
this, the TDA8034HN has a built-in debouncing timer (typically 8 ms).
[3] Uses an internal 11 kΩ pull-up resistor connected to pin VCC.
[4] Uses an internal 20 kΩ pull-up resistor connected to pin VDD.
8. Functional description
Remark: Throughout this document the ISO 7816 terminology conventions have been
adhered to and it is assumed that the reader is familiar with these.
8.1 Power supplies
The power supply voltage ranges are as follows:
• VDDP: 4.85 V to 5.5 V when VCC_SEL2 is HIGH (VCC = 5 V)
• VDDP: 3 V to 5.5 V when VCC_SEL2 is LOW (VCC = 3 V) or when VCC_SEL1 is LOW
(VCC = 1.8 V)
• VDD: 2.7 V to 3.6 V
All interface signals to the system controller are referenced to VDD(INTF). All card contacts
remain inactive during power up or power down. After powering up the device, pin OFFN
remains LOW until pin CMDVCCN is set HIGH and pin PRESN is LOW. During power
down, pin OFFN goes LOW when VDDP falls below the falling threshold voltage (Vth).
The internal oscillator frequency (fosc(int)) is only used during the activation sequences.
When the card is not activated (pin CMDVCCN is HIGH), the internal oscillator is in low
frequency mode to reduce power consumption.
This device has a Low Drop-Off (LDO) voltage regulator connected to pin VCC, and is
used instead of a DC-to-DC converter. It ensures a minimum VCC of 4.75 V and that the
power supply voltage on pin VDDP does not fall below 4.85 V when pin VCC_SEL2 is
HIGH, for a maximum load current of 65 mA.
TDA8034HN_1
Product data sheet
Rev. 01 — 5 February 2010
© NXP B.V. 2010. All rights reserved.
5 of 30
5 Page 
NXP Semiconductors
TDA8034HNwww.DataSheet4U.com
Smart card interface
Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e.
± 25 µs).
CMDVCC
RST
CLK
I/O
VCC
XTAL1
OSCINT
high frequency
t10 t11
t12 t13
tdeact
t14
OSCINT = internal oscillator.
Fig 8. Deactivation sequence
low frequency
001aak995
8.9 VCC regulator
The VCC buffer is able to continuously deliver up to 65 mA at VCC = 5 V, 3 V, or 1.8 V.
The VCC buffer has an internal overload protection with a threshold value of approximately
120 mA. This detection is internally filtered, enabling spurious current pulses up to
200 mA with a duration of a few milliseconds to be drawn by the card without causing
deactivation. However, the average current value must stay below maximum; see Table 8.
8.10 Fault detection
The following conditions are monitored by the fault detection circuit:
• Short-circuit or high current on pin VCC
• Card removal during transaction
• VDDP falling
• VDD falling
• VDD(INTF) falling
• Overheating
Fault detection monitors two different situations:
• Outside card sessions, pin CMDVCCN is HIGH: pin OFFN is LOW if the card is not in
the reader and HIGH if the card is in the reader. Any voltage drop on VDD is detected
by the voltage supervisor. This generates an internal power-on reset pulse but does
not act upon the pin OFFN signal. The card is not powered-up and short-circuits or
overheating are not detected.
TDA8034HN_1
Product data sheet
Rev. 01 — 5 February 2010
© NXP B.V. 2010. All rights reserved.
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