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PDF TDA8034AT Data sheet ( Hoja de datos )
| Número de pieza | TDA8034AT | |
| Descripción | Smart Card Interface | |
| Fabricantes | NXP Semiconductors | |
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TDA8034T; TDA8034AT
Smart card interface
Rev. 01 — 5 February 2010
Product data sheet
1. General description
The TDA8034T/TDA8034AT is a cost-effective analog interface for asynchronous and
synchronous smart cards operating at 5 V or 3 V. Using few external components, the
TDA8034T/TDA8034AT provides all supply, protection and control functions between a
smart card and the microcontroller.
2. Features
I Integrated circuit smart card interface in an SO16 package
I 5 V or 3 V smart card supply
I One protected half-duplex bidirectional buffered I/O line (C7)
I VCC regulation:
N 5 V ± 5 % or 3 V ± 5 % using two low ESR multilayer ceramic capacitors: one of
220 nF and one of 470 nF
N current spikes of 40 nA/s (VCC = 5 V and 3 V) or 15 nA/s (VCC =1.8 V) up to
20 MHz, with controlled rise and fall times and filtered overload detection of
approximately 120 mA
I Thermal and short-circuit protection for all card contacts
I Automatic activation and deactivation sequences triggered by a short-circuit, card
take-off, overheating, falling VDD, VDD(INTF) or VDDP
I Enhanced card-side ElectroStatic Discharge (ESD) protection of > 6 kV
I External clock input up to 26 MHz connected to pin XTAL1
I Card clock generation up to 20 MHz using pin CLKDIV1 with synchronous frequency
changes of:
N 1⁄2 fxtal or 1⁄4 fxtal on TDA8034T
N fxtal or 1⁄2 fxtal on TDA8034AT
I Non-inverted control of pin RST using pin RSTIN
I Compatible with ISO 7816, NDS and EMV 4.2 payment systems
I Supply supervisor for killing spikes during power on and off:
N using a fixed threshold
N using an external resistor bridge with threshold adjustment
I Built-in debouncing on card presence contacts (typically 4.5 ms)
I Multiplexed status signal using pin OFFN
3. Applications
I Pay TV
I Electronic payment
1 page  
NXP Semiconductors
TDA8034T; TDA8034ATwww.DataSheet4U.com
Smart card interface
[5] Uses an internal 20 kΩ pull-up resistor connected to pin VDD.
8. Functional description
Remark: Throughout this document the ISO 7816 terminology conventions have been
adhered to and it is assumed that the reader is familiar with these.
8.1 Power supplies
The power supply voltage ranges are as follows:
• VDDP: 4.85 V to 5.5 V
• VDD: 2.7 V to 3.6 V
All interface signals to the system controller are referenced to VDD(INTF). All card contacts
remain inactive during power up or power down. After powering up the device, pin OFFN
remains LOW until pin CMDVCCN is set HIGH and pin PRESN is LOW. During power
down, pin OFFN goes LOW when VDDP falls below the falling threshold voltage (Vth).
The internal oscillator frequency (fosc(int)) is only used during the activation sequences.
When the card is not activated (pin CMDVCCN is HIGH), the internal oscillator is in low
frequency mode to reduce power consumption.
This device has a Low Drop-Off (LDO) voltage regulator connected to pin VCC, and is
used instead of a DC-to-DC converter. It ensures a minimum VCC of 4.75 V and that the
power supply voltage on pin VDDP does not fall below 4.85 V for a maximum load current
of 65 mA.
8.2 Voltage supervisor
VDD(INTF)
VDD
VDD
REFERENCE
VOLTAGE
VDDP
5 V or 3 V
Fig 3. Voltage supervisor circuit
TDA8034T_TDA8034AT_1
Product data sheet
Rev. 01 — 5 February 2010
001aak991
© NXP B.V. 2010. All rights reserved.
5 of 29
5 Page 
NXP Semiconductors
TDA8034T; TDA8034ATwww.DataSheet4U.com
Smart card interface
• In card sessions, pin CMDVCCN is LOW: when pin OFFN goes LOW, the fault
detection circuit triggers the automatic emergency deactivation sequence (see
Figure 8). When the microcontroller resets pin CMDVCCN to HIGH, after the
deactivation sequence, pin OFFN is rechecked. If the card is still present, pin OFFN
returns to HIGH. This check identifies the fault as either a hardware problem or a card
removal incident.
On card insertion or removal, bouncing can occur in the PRESN signal. This depends on
the type of card presence switch in the connector (normally open or normally closed) and
the mechanical characteristics of the switch. To correct for this, a debouncing feature is
integrated in to the TDA8034T/TDA8034AT. This feature operates at a typical duration of
4.5 ms (tdeb = 640 × (1⁄fosc(int)low). Figure 9 on page 12 shows the operation of the
debouncing feature.
On card insertion, pin OFFN goes HIGH after the debounce time has elapsed. When the
card is extracted, the automatic card deactivation sequence is performed on the first
HIGH/LOW transition on pin PRESN. After this, pin OFFN goes LOW.
OFFN
PRESN
RST
CLK
I/O
VCC
XTAL
OSCINT
high frequency
t10 t12 t13 t14
tdeact
low frequency
Fig 8. Emergency deactivation sequence after card removal
001aai971
TDA8034T_TDA8034AT_1
Product data sheet
Rev. 01 — 5 February 2010
© NXP B.V. 2010. All rights reserved.
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