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PDF W78E051C Data sheet ( Hoja de datos )

Número de pieza W78E051C
Descripción 8-BIT MICROCONTROLLER
Fabricantes Winbond 
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W78E51C/W78E051C Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 2
2. FEATURES ................................................................................................................................. 2
3. PIN CONFIGURATIONS ............................................................................................................ 3
4. PIN DESCRIPTION..................................................................................................................... 4
5. FUNCTIONAL DESCRIPTION ................................................................................................... 5
5.1 New Defined Peripheral.................................................................................................. 5
5.2 Reduce EMI Emission .................................................................................................... 6
5.3 Watchdog Timer ............................................................................................................. 7
5.4 Clock ............................................................................................................................... 8
5.5 Power Management........................................................................................................ 9
5.6 Reset............................................................................................................................... 9
6. SECURITY BITS ....................................................................................................................... 10
6.1 Lock Bit ......................................................................................................................... 10
6.2 MOVC Inhibit................................................................................................................. 11
6.3 Encryption ..................................................................................................................... 11
7. ELECREICAL CHARACTERISTICS......................................................................................... 12
7.1 Absolute Maximum Ratings .......................................................................................... 12
7.2 D.C. Characteristics...................................................................................................... 12
7.3 A.C. Characteristics ...................................................................................................... 14
7.3.1 Clock Input Waveform ....................................................................................................14
7.3.2 Program Fetch Cycle......................................................................................................14
7.3.3 Data Read Cycle ............................................................................................................15
7.3.4 Data Write Cycle.............................................................................................................15
7.3.5 Port Access Cycle ..........................................................................................................15
7.3.6 Program Operation .........................................................................................................16
8. TIMING WAVEFORMS ............................................................................................................. 17
8.1 Program Fetch Cycle .................................................................................................... 17
8.2 Data Read Cycle........................................................................................................... 17
8.3 Data Write Cycle ........................................................................................................... 18
8.4 Port Access Cycle......................................................................................................... 18
9. TYPICAL APPLICATION CIRCUITS ........................................................................................ 19
9.1 Expanded External Program Memory and Crystal ....................................................... 19
9.2 Expanded External Data Memory and Oscillator ......................................................... 20
10. PACKAGE DIMENSIONS ......................................................................................................... 21
10.1 40-pin DIP ..................................................................................................................... 21
10.2 44-pin PLCC ................................................................................................................. 21
10.3 44-pin PQFP ................................................................................................................. 22
11. REVISION HISTORY ................................................................................................................ 23
Publication Release Date: November 10, 2006
- 1 - Revision A4

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W78E051C pdf
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W78E51C/W78E051C
5. FUNCTIONAL DESCRIPTION
The W78E051C architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
5.1 New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3 EX3 IE3
IT3 PX2 EX2 IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Seven-source interrupt information
INTERRUPT SOURCE
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
External Interrupt 2
External Interrupt 3
VECTOR
ADDRESS
03H
0BH
13H
1BH
23H
33H
3BH
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
0 (highest)
1
2
3
4
5
6 (lowest)
ENABLE
REQUIRED
SETTINGS
IE.0
IE.1
IE.2
IE.3
IE.4
XICON.2
XICON.6
INTERRUPT TYPE
EDGE/LEVEL
TCON.0
-
TCON.2
-
-
XICON.0
XICON.3
Publication Release Date: November 10, 2006
- 5 - Revision A4

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W78E51C/W78E051C
6.2 MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
6.3 Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
- 11 -
Publication Release Date: November 10, 2006
Revision A4

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