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PDF IDT72V281 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V281 | |
| Descripción | (IDT72V281 / IDT72V291) 3.3 VOLT CMOS SuperSync FIFOTM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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3.3 VOLT CMOS SuperSync FIFO™
65,536 x 9
131,072 x 9
www.DaItaDShTee7t42UV.co2m81
IDT72V291
.EATURES:
• Choose among the following memory organizations:
IDT72V281
65,536 x 9
IDT72V291
131,072 x 9
• Pin-compatible with the IDT72V261/72V271 SuperSync FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable
settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write clocks (permit reading and writing
simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin
Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
• Industrial Temperature Range (-40°C to + 85°C) is available
DESCRIPTION:
The IDT72V281/72V291 are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:
• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)
.UNCTIONAL BLOCK DIAGRAM
WEN WCLK
D0-D8
LD SEN
WRITE CONTROL
LOGIC
WRITE POINTER
INPUT REGISTER
RAM ARRAY
65,536 x 9
131,072 x 9
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
MRS
PRS
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
RCLK
REN
Q0-Q8
OE
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
2001 Integrated Device Technology, Inc.
1
4513 drw 01
APRIL 2001
DSC-4513/1
1 page  
IDT72V281/72V291
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM
TSTG
IOUT
Rating
Terminal Voltage
with respect to GND
Storage
Temperature
DC Output Current
Commercial
–0.5 to +4.6
–55 to +125
–50 to +50
Unit
V
°C
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPwEwwR.DAatTaSIhNeeGt4U.com
CONDITIONS
Symbol
Parameter
Min. Typ. Max. Unit
VCC Supply Voltage(Com’l & Ind’’l) 3.0 3.3
3.6
V
GND Supply Voltage(Com’l & Ind’l) 0
0
0
V
VIH Input High Voltage
(Com’l & Ind’l)
VIL(1) Input Low Voltage
(Com’l & Ind’l)
TA OperatingTemperature
Commercial
TA OperatingTemperature
Industrial
2.0 — VCC + 0.5 V
— — 0.8
0 — 70
V
OC
-40
85
°C
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0oC to +70oC; Industrial: VCC = 3.3V ± 0.3V, TA= -40°C to +85°C)
IDT72V281L
IDT72V291L
Com’l & Ind’l (1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min. Max. Unit
ILI(2) InputLeakageCurrent
ILO(3) OutputLeakageCurrent
–1 1 µ A
–10 10 µA
VOH
VOL
ICC1(4,5,6)
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
2.4 — V
— 0.4 V
— 55 mA
ICC2(4,7)
NOTES:
Standby Current
— 20 mA
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 11 + 1.65*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25oC, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL
= capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25oC, f = 1.0MHz)
Symbol
CIN(2)
COUT(1,2)
Parameter(1)
Input
Capacitance
Output
Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
10
10
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
Unit
pF
pF
5
5 Page 
IDT72V281/72V291
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
the read pointer to the first location of memory, then the actual retransmit,
which consists of reading out the memory contents, starting at the beginning
of memory.
Retransmit setup is initiated by holding RT LOW during a rising RCLK
edge. REN and WEN must be HIGH before bringing RT LOW. At least
one word, but no more than D - 2 words should have been written into the
FIFO between Reset (Master or Partial) and the time of Retransmit setup.
D = 65,536 for the IDT72V281 and D = 131,072 for the IDT72V291 in IDT
Standard mode. In FWFT mode, D = 65,537 for the IDT72V281 and
D = 131,073 for the IDT72V291.
If IDT Standard mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting EF LOW. The change in level will only be
noticeable if EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read opera-
tions may begin starting with the first location in memory. Since IDT
Standard mode is selected, every wordwrewawd.DinactluadSihnegetth4eU.fcirostmword
following Retransmit setup requires a LOW on REN to enable the rising
edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for
the relevant timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time,
the contents of the first location appear on the outputs. Since FWFT mode
is selected, the first word appears on the outputs, no LOW on REN is
necessary. Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
For either IDT Standard mode or FWFT mode, updating of the PAE,
HF and PAF flags begin with the rising edge of RCLK that RT is setup.
PAE is synchronized to RCLK, thus on the second rising edge of RCLK
after RT is setup, the PAE flag will be updated. HF is asynchronous, thus
the rising edge of RCLK that RT is setup will update HF. PAF is
synchronized to WCLK, thus the second rising edge of WCLK that occurs
tSKEW after the rising edge of RCLK that RT is setup will update PAF. RT
is synchronized to RCLK.
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet IDT72V281.PDF ] | |
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