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PDF LC680100A Data sheet ( Hoja de datos )
| Número de pieza | LC680100A | |
| Descripción | 32-Bit RISC Microcontroller | |
| Fabricantes | Sanyo Semicon Device | |
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Ordering number : ENN*6830
CMOS IC
LC680100A
32-Bit RISC Microcontroller
Preliminary
Overview
The LC680100A is a 32 bit microcontroller developed exclusively by Sanyo, based on a 32 bit RISC CPU and
incorporating on a single chip a high speed multiplier, 2kB of cache RAM, 2kB data RAM, DRAM control unit, external
memory control unit and peripheral
It is an ideal control device for digital cameras, color printers and hand held data terminals.
Features
(1) CPU core
:32 bit RISC (Speed: 15MHz, Instruction cycle time: 67ns)
(2) High Speed Multiplier
:16bit x 16bit (in 1 instruction cycle)
(3) Instruction cache RAM :2kB (512x32bit)
(4) Data RAM
:2kB (512x32bit)
(5) DRAM Control Unit
(6) External memory bus control unit
(7) I/O port
:One 16 bit I/O port, one 8 bit I/O port
(8) UART
:Two full duplex asynchronous channels (one channel has 16bit FIFO)
(9) Serial I/O
:One three-wire synchronous clock, 8 bit
(10) Timer
:4 channels (TM0 = 16bit + 16bit)
(TM1, TM2, TM3 = 8bit + 8bit)
(11) PWM Output
:Three 8 bit resolution outputs (Common with TM1, TM2, TM3)
(12) Interrupt controller
:13 source events (5 internal, 8 external), 5 vectored
(13) OSC circuit
:Two types: main and RC. VCO/PLL is built-in, frequency multiplication possible.
(14) Standby
:Standby (HOLD) and sleep (HALT) modes available
(15) VDD
:3.3V typ.
Package and Pins
SQFP100, 100 pins
Development tools
A C compiler, assembler and emulator are available to be run on a PC.
Ver.1.2
D0798
N3000 RM (IM) IT No.6830-1/16
1 page  
Pin Number
Pin Name
33 NMI
35 P10/BGNT
36 P11/RAS
37 P12/CASU
38 P13/CASL
39 P14/DMXS
40 P15/RFREQ
41 P16/IRQOT
42 P17/MCLK/HOLD0
44
45 to 54,
56 to 69
70
71
72
74 to 81,
83 to 90
92
93
94
95
96
97
98
99
100
A0/LBS
A1to A24
A25/CS5
A26/CS4
A27/CS3
D0 to D15
CS0
CS1
CS2
CS6
RD
WRU/UBS
WRL/WR
WAIT
BREQ
LC680100A
I/O Function Description
I NMI interrupt
I/O PORT1 bit0 input.
Also bus grant output.
I/O PORT1 bit1 input. Also
DRAM control RAS signal out.
I/O PORT1 bit2 input. Also
DRAM control CASU signal out.
I/O PORT1 bit3 input. Also
DRAM control CASL signal out.
I/O PORT1 bit4 input. Also
DRAM control DMXS signal out.
I/O PORT1 bit5 input. Also
DRAM control RFREQ I/O.
I/O PORT1 bit6 input.
Also IRQOT output.
I/O PORT1 bit7 input.
MCLK output,
HOLD state output
I/O Bus Address bit0 or
Lower byte strobe signal.
I/O Bus Address bit1 to 24.
Pin Format
Schmitt Input
Schmitt Input•Tristate
output
Schmitt Input•PU
Output
Schmitt Input•Tristate
output
Schmitt Input•Tristate
output
I/O Bus Address bit25 or CS5.
I/O Bus Address bit26 or CS4
I/O Bus Address bit27 or CS3.
I/O Bus data bit0 to 15
Schmitt Input•Tristate
output
I/O CS0
I/O CS1
Schmitt Input•Tristate
output
I/O CS2
I/O CS6
I/O Bus read signal.
Schmitt Input•Tristate
output
I/O Upper byte write signal or Upper byte strobe.
I/O Upper byte write signal or Write.
I/O Bus cycle wait
I Bus request.
Schmitt Input•PU
output
Schmitt Input
No.6830-5/16
5 Page 
LC680100A
6. DRAM Timing at Ta = -20 to 70°C, VSS = 0V, VDD = 3.0 to 3.6V, with the load in Figure 14
Parameter
Symbol
Address (ROW) delay
time
Address (COL) delay
time
Address (COL) hold
time
RAS delay time
RAS hold time
DMXS delay time
DMXS hold time
CASL•CASU delay
time
CASL•CASU hold
time
Read data set up time
(2)
Read data hold time
(2)
WRL•WRU delay
time
WRL•WRU hold time
Write data delay time
(2)
Write data hold time
(2)
tAROW
tACOL
tCOLA
tARAS
tRASA
tDMXSR
tDMXSC
tACAS(L/U)
tCAS(L/U)A
tsRD2
thRD2
tAWR(L/U)
tWR(L/U)A
tdWD2
thWD2
Pins
A27 to A0
Conditions
Ratings
Min. Typ. Max.
Figure 9, Figure 10
75
A27 to A0
Figure 9, Figure 10
55
A27 to A0
RAS
RAS
DMXS
DMXS
CASU, CASL
Figure 9, Figure 10
Figure 9, Figure 10
Figure 9, Figure 10
Figure 9, Figure 10
Figure 9, Figure 10
Figure 9, Figure 10
70
65
50
70
50
65
CASU, CASL
Figure 9, Figure 10
50
D15 to D0
Figure 9
30
D15 to D0, RD Figure 9
0
WRU, WRL
WRU, WRL
D15 to D0,
WRU, WRL
D15 to D0,
WRU, WRL
Figure 10
Figure 10
Figure 10
Figure 10
0
45
50
70
Unit
ns
ns
ns
Table 1. Guaranteed Value for the Ceramic Oscillators
Oscillator
Manufacturer
Oscillator
4MHZ (External Capacitor)
4MHZ (Capacitor built-in)
8MHZ (External Capacitor)
8MHZ (Capacitor built-in)
Murata
CSA4. OOMG
CST4. OOMGW
CSA8. OOMTZ
CST8. OOMTW
C1
33pF
(30pF)
33pF
(30pF)
C2
33pF
(30pF)
33pF
(30pF)
No.6830-11/16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LC680100A.PDF ] | |
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