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PDF DS16EV5110A Data sheet ( Hoja de datos )
| Número de pieza | DS16EV5110A | |
| Descripción | Video Equalizer | |
| Fabricantes | National Semiconductor Corporation | |
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DS16EV5110A
April 6, 2009
www.DataSheet4U.com
Video Equalizer (3D+C) for DVI, HDMI Source/Repeater/
Sink Applications
General Description
The DS16EV5110A is a multi-channel equalizer optimized for
video cable extension Source/Repeater/Sink Applications. It
operates between 250Mbps and 2.25Gbps with common ap-
plications at 1.65Gbps and 2.25Gbps (per data channel). It
contains three Transition-Minimized Differential Signaling
(TMDS) data channels and one clock channel as specified for
DVI and HDMI interfaces. It provides compensation for skin-
effect and dielectric losses, a common phenomenon when
transmitting video on commercially available high definition
video cables.
The inputs conform to DVI and HDMI requirements and fea-
tures programmable levels of input equalization. The pro-
grammable levels of equalization provide optimal signal boost
and reduces inter-symbol interference. Eight levels of boost
are selectable via a pin interface or by the optional System
Management Bus.
The clock channel is optimized for clock rates of up to 225
MHz and features a signal detect circuit. To maximize noise
immunity, the DS16EV5110A features a signal detector with
programmable thresholds. The threshold is adjustable
through a System Management Bus (SMBus) interface.
The DS16EV5110A may be used in Source Applications, Sink
Applications, or as a Repeater.
The DS16EV5110A also provides support for system power
management via output enable controls. Additional controls
are provided via the SMBus enabling customization and op-
timization for specific applications requirements. These con-
trols include programmable features such as output ampli-
tude and boost controls as well as system level diagnostics.
The DS16EV5110A is a pin-for-pin replacement to the
DS16EV5110. It features an enhanced CML output that
presents a high impedance when powered down.
Features
■ 8 levels of equalization settable by 3 pins or through the
SMBus interface
■ DC-Coupled inputs and outputs
■ Optimized for operation from 250 Mbps to 2.25 Gbps in
support of UXGA, 480 I/P, 720 I/P, 1080 I, and 1080 P with
8, 10, and 12–bit Color Depth Resolutions
■ Two DS16EV5110A devices support DVI/HDMI Dual Link
■ DVI 1.0, and HDMI 1.3a Compatible TMDS Interface
■ Clock channel signal detect (LOS)
■ Enable for power savings standby mode
■ System Management Bus (SMBus) provides control of
boost, output amplitude, enable, and clock channel signal
detect threshold
■ Low power consumption: 475mW (Typical)
■ 0.13 UI total jitter at 1.65 Gbps including cable
■ Single 3.3V power supply
■ Small 7mm x 7mm, 48-pin leadless LLP package
■ -40°C to +85°C operating temperature range
■ Extends TMDS cable reach over:
1. > 40 meters 24 AWG DVI Cable (1.65Gbps)
2. > 20 meters 28 AWG DVI Cable (1.65Gbps)
3. > 20 meters Cat5/Cat5e/Cat6 cables (1.65Gbps)
4. > 20 meters 28 AWG HDMI cables (2.25Gbps)
Applications
■ HDMI / DVI Cable Extenders
■ HDMI / DVI Switches
■ Projectors
■ High Definition Displays
Typical Application
© 2009 National Semiconductor Corporation 300646
30064653
www.national.com
1 page  
Symbol
tCCSK
Parameter
Inter Pair Channel-to-Channel
Skew (all 4 Channels)
tD Latency
OUTPUT JITTER
TJ1 Total Jitter at 1.65 Gbps
TJ2 Total Jitter at 2.25 Gbps
TJ3 Total Jitter at 165 MHz
TJ4 Total Jitter at 225 MHz
RJ
BIT RATE
FCLK
BR
Random Jitter
Clock Frequency
Bit Rate
Conditions
Difference in 50% crossing
between shortest and longest
channels
20m 28 AWG STP DVI Cable
Data Paths
EQ Setting 0x04 PRBS7
(Notes 5, 6, 7)
20m 28 AWG STP DVI Cable
Data Paths
EQ Setting 0x04 PRBS7
(Notes 5, 6, 7)
Clock Paths
Clock Pattern
(Notes 5, 6, 7)
Clock Paths
Clock Pattern
(Notes 5, 6, 7)
(Notes 7, 8)
Clock Path
(Note 5)
Data Path
(Note 5)
Min Typ Max Units
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25 ps
350 ps
0.13
0.17
UIP-P
0.2 UIP-P
0.165
UIP-P
25
0.25
0.165
3
225
2.25
UIP-P
psrms
MHz
Gbps
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of –40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at VDD = 3.3V, TA = 25°C, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes.
Note 4: Allowed supply noise (mVP-P sine wave) under typical conditions.
Note 5: Specification is guaranteed by characterization and is not tested in production.
Note 6: Deterministic jitter is measured at the differential outputs (TPC of Figure 2), minus the deterministic jitter before the test channel (TPA of Figure 2). Random
jitter is removed through the use of averaging or similar means.
Note 7: Total Jitter is defined as peak-to-peak deterministic jitter from (Note 8) + 14.2 times random jitter in psrms.
Note 8: Random jitter contributed by the equalizer is defined as sq rt (JOUT2 − JIN2). JOUT is the random jitter at equalizer outputs in psrms, see TPC of Figure 2;
JIN is the random jitter at the input of the equalizer in psrms, see TPA of Figure 2.
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5 Page 
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FIGURE 3. DS16EV5110A Data Channel
30064637
FIGURE 4. DS16EV5110A Clock Channel
30064638
OUTPUT LEVEL CONTROL
The output amplitude of the TMDS drivers for both the data
channels and the clock channel can be controlled via the SM-
Bus (see Table 1). The default output level is 1000mV p-p.
The following Table presents the output level values support-
ed:
TABLE 5. Output Level Control Settings – REG 0x08[3:2]
Bit 3
Bit 2
Output Level (mV)
00
540
01
770
10
1000 (default)
11
1200
AUTOMATIC ENABLE FEATURE
It may be desired for the DS16EV5110A to be configured to
automatically enter STANDBY mode if no clock signal is
present. STANDBY mode can be implemented by connecting
the Signal Detect (SD) pin to the external (LVCMOS) Enable
(EN) pin. In order for this option to function properly,
REG07[0] should be set to a “0” (default value). If the clock
signal applied to the clock channel input swings above the
SD_ON threshold specified in the threshold register via the
SMBus, then the SD pin is asserted High. If the SD pin is
connected to the EN pin, this will enable the equalizer, limiting
amplifier, and output buffer on the data channels and the lim-
iting amplifier and output buffer on the clock channel; thus the
DS16EV5110A will automatically enter the ACTIVE state. If
the clock signal present falls below SD_OFF threshold spec-
ified in the threshold register, then the SD pin will be asserted
Low, causing the aforementioned blocks to be placed in the
STANDBY state.
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| PDF Descargar | [ Datasheet DS16EV5110A.PDF ] | |
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