DataSheet.es    


PDF IDT723666 Data sheet ( Hoja de datos )

Número de pieza IDT723666
Descripción (IDT7236x6) CMOS TRIPLE BUS SyncFIFOTM
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



Hay una vista previa y un enlace de descarga de IDT723666 (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! IDT723666 Hoja de datos, Descripción, Manual

CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING
www.DataSheet4U.com
2,048 x 36 x 2
IDT723656
4,096 x 36 x 2
IDT723666
8,192 x 36 x 2
IDT723676
FEATURES
Memory storage capacity:
IDT723656 – 2,048 x 36 x 2
IDT723666 – 4,096 x 36 x 2
IDT723676 – 8,192 x 36 x 2
Clock frequencies up to 83 MHz (8ns access time)
Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1024)
Serial or parallel programming of partial flags
Big- or Little-Endian format for word and byte bus sizes
Loopback mode on Port A
Retransmit Capability
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Pin compatible to the lower density parts, IDT723626/3636/3646
Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
LOOP
MRS1
PRS1
FFA/IRA
AFA
FS2
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
36
RT1
RTM
RT2
36
FIFO1 and
FIFO2
Retransmit
Logic
MBF2
Mail 1
Register
36
RAM ARRAY
2,048 x 36
36
4,096 x 36
8,192 x 36
FIFO1
Write
Pointer
Read
Pointer
Status Flag
Logic
Programmable Flag
Offset Registers
Timing
Mode
13
FIFO2
Status Flag
Logic
Read
Pointer
Write
Pointer
RAM ARRAY
36 2,048 x 36
4,096 x 36
8,192 x 36
36
Mail 2
Register
MBF1
18
B0-B17
Port-B
Control
Logic
CLKB
RENB
CSB
MBB
SIZEB
Common
Port
Control
Logic
(B and C)
EFB/ORB
AEB
BE
FWFT
FFC/IRC
AFC
FIFO2,
Mail2
Reset
Logic
18
Port-C
Control
Logic
MRS2
PRS2
C0-C17
CLKC
WENC
MBC
SIZEC
5611 drw01
IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-5611/4

1 page




IDT723666 pdf
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O
Description
www.DataSheet4U.com
FS0/SD FlagOffsetSelect0/ I FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During Master Reset,
Serial Data
FS1/SEN and FS0/SD, together with FS2, select the flag offset programming method. Three Offset register
programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or 1,024),
FS1/SEN FlagOffsetSelect1/ I parallel load from Port A, and serial load.
Serial Enable
FS2(1)
When serial load is selected for flag Offset register programming, FS1/SEN is used as an enable synchronous to
FlagOffsetSelect2 I the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on
FS0/SD into the X and Y registers. The number of bit writes required to program the Offset registers is 44 for the
IDT723656, 48 for the IDT723666, and 52 for the IDT723676. The first bit write stores the Y-register (Y1) MSB
and the last bit write stores the X-register (X2) LSB.
LOOP
Loopback Select
I This pin selects the loopback feature for Port A. During Loopback data from FIFO2 will be directed to the input of
FIFO1. to initiate a Loop the LOOP pin must be held LOW and the ENA pin must be HIGH.
MBA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
Select
outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects
FIFO2 output-register data for output.
MBB Port B Mailbox I A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are
Select
active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1 output
register data for output.
MBC Port C Mailbox I A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during
Select
Master Reset.
MBF1
Mail1 Register
Flag
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1
register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
MRS1
Mail2 Register
Flag
Master Reset
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the mail2 register. Writes to the mail2
register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a
Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method (serial or
parallel) and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures ports B and
C for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH
transitions of CLKB must occur while MRS1 is LOW.
MRS2 MasterReset
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with MRS1, selects
the programming method (serial or parallel) and one of the five flag default offsets for FIFO2. Four LOW-to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKC must occur while MRS2 is LOW.
PRS1/
RT1
Partial Reset/
Retransmit FIFO1
I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. If RTM
is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read and write
pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently
selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are
all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read pointer only to
the first memory location.
PRS2/
RT2
Partial Reset/
Retransmit FIFO2
I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. If RTM
is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read and write
selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are
all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO2 read pointer only to
the first memory location.
RENB
RTM
Port B Read Enable I RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on Port B.
RetransmitMode I This pin is used in conjunction with the RT1 and RT2 pins. When RTM is HIGH a Retransmit is performed on FIFO1
or FIFO2 respectively.
5

5 Page





IDT723666 arduino
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
SIGNAL DESCRIPTION
MASTER RESET ( MRS1, MRS2 )
After power up, a Master Reset operation must be performed by providing
a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, the FIFO1
memory of the IDT723656/723666/723676 undergoes a complete reset by
takingitsassociatedMasterReset(MRS1)inputLOWforatleastfourPortAClock
(CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2
memory undergoes a complete reset by taking its associated Master Reset
(MRS2) input LOW for at least four Port A Clock (CLKA) and four Port C Clock
(CLKC) LOW-to-HIGH transitions. The Master Reset inputs can switch
asynchronouslytotheclocks. AMasterResetinitializestheassociatedreadand
write pointers to the first location of the memory and forces the Full/Input Ready
flag (FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/
ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW and the Almost-Full flag
(AFA, AFC) HIGH. A Master Reset also forces the associated Mailbox Flag
(MBF1,MBF2)oftheparallelmailboxregisterHIGH. AfteraMasterReset,the
FIFO'sFull/InputReadyflagissetHIGHaftertwoWriteClockcycles. Thenthe
FIFO is ready to be written to.
A LOW-to-HIGH transition on the FIFO1 Master Reset (MRS1) input latches
the value of the Big-Endian (BE) input for determining the order by which bytes
aretransferredthroughPortsBandC. ItalsolatchesthevaluesoftheFlagSelect
(FS0, FS1 and FS2) inputs for choosing the Almost-Full and Almost-Empty
offsets and programming method.
A LOW-to-HIGH transition on the FIFO2 Master Reset (MRS2) clears the flag
offset registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the FIFO2
Master Reset (MRS2) together with the FIFO1 Master Reset input (MRS1)
latches the value of the Big-Endian (BE) input for Ports B and C and also latches
the values of the Flag Select (FS0, FS1 and FS2) inputs for choosing the Almost-
Full and Almost-Empty offsets and programming method (for details see Table
1,FlagProgramming, andAlmost-EmptyandAlmost-Fullflagoffsetprogram-
ming section). The relevant Master Reset timing diagrams can be found in
Figure 4 and 5.
Note that MBC must be HIGH during Master Reset (until FFA/IRA and
FFC/IRC go HIGH). MBA and MBB are "don't care" inputs1 during Master
Reset.
PARTIAL RESET (PRS1, PRS2)
The FIFO1 memory of these devices undergoes a limited reset by taking its
associated Partial Reset (PRS1) input LOW for at least four Port A Clock (CLKA)
and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2 memory
undergoes a limited reset by taking its associated Partial Reset (PRS2) input
LOW for at least four Port A Clock (CLKA) and four Port C Clock (CLKC) LOW-
to-HIGH transitions. The RTM pin must be LOW during the time of partial reset.
ThePartialResetinputscanswitchasynchronouslytotheclocks. APartialReset
initializes the internal read and write pointers and forces the Full/Input Ready
flag (FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/
ORB)LOW,theAlmost-Emptyflag(AEA, AEB)LOW,andtheAlmost-Fullflag
(AFA, AFC)HIGH. APartialResetalsoforcestheMailboxFlag(MBF1,MBF2)
oftheparallelmailboxregisterHIGH. AfteraPartialReset,theFIFO’sFull/Input
Ready flag is set HIGH after two Write Clock cycles.
Whatever flag offsets, programming method (parallel or serial), and timing
mode (FWFT or IDT Standard mode) are currently selected at the time a Partial
Resetisinitiated,thosesettingswill remainunchangeduponcompletionofthe
resetoperation. APartialResetmaybeusefulinthecasewherereprogramming
a FIFO following a Master Reset would be inconvenient. See Figure 6 and 7
for Partial Reset timing diagrams.
RETRANSMIT ( RT1, RT2 )
www.DataSheet4U.com
The FIFO1 memory of these devices undergoes a Retransmit by taking its
associated Retransmit (RT1) input LOW for at least four Port A Clock (CLKA)
and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit
initializes the read pointer of FIFO1 to the first memory location.
The FIFO2 memory undergoes a Retransmit by taking its associated
Retransmit (RT2) input LOW for at least four Port A Clock (CLKA) and four Port
CClock(CLKC)LOW-to-HIGHtransitions. TheRetransmitinitializestheread
pointer of FIFO1 to the first memory location.
TheRTMpinmustbeHIGHduringthetimeofRetransmit. Notethatthe RT1
input is muxed with the PRS1 input, the state of the RTM pin determining whether
this pin performs a Retransmit or Partial Reset. Also, the RT2 input is muxed
with the PRS2 input, the state of the RTM pin determining whether this pin
performs a Retransmit or Partial Reset. See Figures 30, 31, 32 and 33 for
Retransmit timing diagrams.
BIG-ENDIAN/FIRST WORD FALL THROUGH ( BE/FWFT )
— ENDIAN SELECTION
Thisisadualpurposepin. AtthetimeofMasterReset,theBEselectfunction
is active, permitting a choice of Big- or Little-Endian byte arrangement for data
written to Port C or read from Port B. This selection determines the order by
which bytes (or words) of data are transferred through those ports. For the
followingillustrations,notethatbothportsB andCareconfiguredtohaveabyte
(or a word) bus size.
A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs
go from LOW to HIGH will select a Big-Endian arrangement. When data is
moving in the direction from Port A to Port B, the most significant byte (word) of
the long word written to Port A will be read from Port B first; theleastsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast. When
data is moving in the direction from Port C to Port A, the byte (word) written to
Port C first will be read from Port A as the most significant byte (word) of the long
word; the byte (word) written to Port C last will be read from Port A as the least
significant byte (word) of the long word.
A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs
go from LOW to HIGH will select a Little-Endian arrangement. When data is
moving in the direction from Port A to Port B, the least significant byte (word) of
the long word written to Port A will be read from Port B first; the most significant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast. When
data is moving in the direction from Port C to Port A, the byte (word) written to
Port C first will be read from Port A as the least significant byte (word) of the long
word; the byte (word) written to Port C last will be read from Port A as the most
significantbyte(word)ofthelongword. RefertoFigure2and3forillustrations
of the BE function. See Figure 4 (FIFO1 Master Reset) and 5 (FIFO2 Master
Reset) for Endian Select timing diagrams.
— TIMING MODE SELECTION
After Master Reset, the FWFT select function is available, permitting a choice
between two possible timing modes: IDT Standard mode or First Word Fall
Through(FWFT)mode. OncetheMasterReset(MRS1, MRS2)inputisHIGH,
a HIGH on the BE/FWFT input during the next LOW-to-HIGH transition of CLKA
(for FIFO1) and CLKC (for FIFO2) will select IDT Standard mode. This mode
uses the Empty Flag function (EFA, EFB) to indicate whether or not there are
any words present in the FIFO memory. It uses the Full Flag function (FFA,
FFC) to indicate whether or not the FIFO memory has any free space for writing.
In IDT Standard mode, every word read from the FIFO, including the first, must
be requested using a formal read operation.
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
11

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet IDT723666.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
IDT723662(IDT7236x2) CMOS SyncBiFIFOIDT
IDT
IDT723663(IDT7236x3) CMOS SyncFIFO WITH BUS-MATCHINGIntegrated Device Technology
Integrated Device Technology
IDT723664(IDT7236x4) CMOS SyncBiFIFOIDT
IDT
IDT723666(IDT7236x6) CMOS TRIPLE BUS SyncFIFOTMIntegrated Device Technology
Integrated Device Technology

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar