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Número de pieza | EZ80190 | |
Descripción | high-performance Ethernet module | |
Fabricantes | Zilog | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de EZ80190 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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eZ801905050MOD
eZ80190 Module
Product Specification
PS019101-1003
PRELIMINARY
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
1 page eZ801905050MOD
eZ80190 Module Product wSwpwe.cDiaftiacShaeteito4Un.com
v
List of Tables
Table 1. eZ80190 Module Peripheral Bus Connector Pin Identification. . . . . . . . 5
Table 2. eZ80190 Module I/O Connector Pin Identification . . . . . . . . . . . . . . . . . 8
Table 3. Ethernet Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Chip Frequency to Wait State Cycle Time Calculation. . . . . . . . . . . . . 14
Table 5. Real-Time Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PS019101-1003
PRELIMINARY
List of Tables
5 Page eZ801905050MOD
eZ80190 Module Product wSwpwe.cDiaftiacShaeteito4Un.com
6
Table 1. eZ80190 Module Peripheral Bus Connector Pin Identification* (Continued)
Pin # Symbol
Pull
Up/Down* Signal Direction Comments
23 A18
Bidirectional
24 A16
Bidirectional
25 A19
Bidirectional
26 GND
27 A2
Bidirectional
VSS/Ground (0V).
28 A1
Bidirectional
29 A11
Bidirectional
30 A12
Bidirectional
31 A4
Bidirectional
32 A20
Bidirectional
33 A5
Bidirectional
34 A17
Bidirectional
35 Reserved
36 DIS_Flash
PU 10KΩ Input
A Low disables onboard Flash memory.
Flash is enabled if DIS_Flash is not
connected; CMOS Input 3.3V (5V tolerant).
37 A21
Bidirectional
38 VCC
39 A22
Bidirectional
3.3V supply input pin.
40 A23
Bidirectional
41 CS0
Output
42 CS1
Output
43 CS2
Output
44 D0
PU 4k7Ω Bidirectional
45 D1
PU 4k7Ω Bidirectional
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.
PS019101-1003
PRELIMINARY
I/O Connector (JP2)
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet EZ80190.PDF ] |
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