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PDF IR3505 Data sheet ( Hoja de datos )
| Número de pieza | IR3505 | |
| Descripción | XPHASE3TM PHASE IC | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IR3505 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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IR3505
DATA SHEET
XPHASE3TM PHASE IC
DESCRIPTION
The IR3505 Phase IC combined with an IR XPhase3TM Control IC provides a full featured and flexible way to
implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides
overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single
phase of a multiphase converter. The XPhase3TM architecture results in a power supply that is smaller, less
expensive, and easier to design while providing higher efficiency than conventional approaches.
FEATURES
• 7V/2A gate drivers (4A GATEL sink current)
• Support converter output voltage up to 5.1 V (Limited to VCCL-1.4V)
• Support loss-less inductor current sensing
• Feed-forward voltage mode control
• Integrated boot-strap synchronous PFET
• Only four IC related external components per phase
• 3 wire analog bus connects Control and Phase ICs (VDAC, Error Amp, ISHARE)
• 3 wire digital bus for accurate daisy-chain phase timing control without external components
• Debugging function isolates phase IC from the converter
• Self-calibration of PWM ramp, current sense amplifier, and current share amplifier
• Single-wire bidirectional average current sharing
• Small thermally enhanced 16L 3 x 3mm MLPQ package
• RoHS compliant
APPLICATION CIRCUIT
12V
www.DataSheet4U.com
CCS
RCS
6 Wire
Bus to
Control
IC
1 ISHARE
SW 12
2
3
IR3505
DACIN
GATEH
PHASE
LGND IC
BOOST
11
10
CBST
4 PHSIN
VCCL 9
VCCL
Page 1 of 19
CVCCL
CIN
L
VOUT+
COUT
VOUT-
Mar 04th, 2008
1 page  
IR3505
PARAMETER
TEST CONDITION
OVP Comparator
OVP Threshold
Step V(ISHARE) up until GATEL drives
high. Compare to V(VCCL)
Propagation Delay
V(VCCL)=5V, Step V(ISHARE) up from
V(DACIN) to V(VCCL). Measure time to
V(GATEL)>4V.
Synchronous Rectification Disable Comparator
Threshold Voltage
The ratio of V(CSIN-) / V(DACIN), below
which V(GATEL) is always low.
Negative Current Comparator
Input Offset Voltage
Note 1
Propagation Delay Time
Apply step voltage to V(CSIN+) –
V(CSIN-). Measure time to V(GATEL)<
1V.
Bootstrap Diode
Forward Voltage
I(BOOST) = 30mA, VCCL=6.5V
Debug Comparator
Threshold Voltage
Compare to V(VCCL)
General
VCC Supply Current
VCCL Supply Current
BOOST Supply Current
4.75V ≤ V(BOOST)-V(SW) ≤ 8V
DACIN Bias Current
SW Bias Current
MIN
-1.0
15
66
-16
100
180
-250
1.1
3.1
1.2
-1.5
-0.5
TYP
-0.8
40
75
0
200
260
-150
3.0
6.7
3.5
-0.75
-1.8
MAX
-0.4
70
86
16
400
480
-50
6.1
12.1
5.8
1
-2.9
UNIT
V
nS
%
mV
nS
mV
mV
mA
mA
mA
µA
mA
www.DaNtaoSthee1et:4UG.cuoamranteed by design, but not tested in production
Note 2: VCCL-0.5V or VCC – 2.5V, whichever is lower
Page 5 of 19
Sept 26th, 2007
5 Page 
IR3505
IR3505 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3505 is shown in Figure 5, and specific features are discussed in the following sections.
CLKIN
PHSIN
EAIN
VCC
100% DUTY LATCH
PWMQ
CLK Q
PWM_CLK
D
PWM COMPARATOR
-
+
RMPOUT
PHSIN
VCC
CALIBRATION
DACIN-SHARE_ADJ
PWM RAMP
GENERATOR
PWM LATCH
DQ
PWM_CLK
CLK Q
RESET
DOMINANT
PWM RESET
VCCL
ISHARE
DACIN
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BODY BRAKING
100mV COMPARATOR
200mV
NEGATIVE
DACIN +
-
SHARE_ADJ
DEBUG OFF
(LOW=OPEN)
CURRENT
OVP LATCH
COMPARATOR
VCCL
-
0.8V
QR
+
RESET
S
DOMINANT
SHARE
ADJUST
NEGATIVE CURRENT
COMPARATOR
AMPLIFIER
3K
-
+
CALIBRATION
PHSIN(CLKIN IF 1-PHASE)
PWMQ
CLK Q
D
GATEH
DRIVER
GATEH NON-
OVERLAP
LATCH
QS
SET R
DOMINANT
GATEL NON-
OVERLAP
LATCH
QS
SET R
DOMINANT
GATEH NON-
OVERLAP
COMPARATOR
-
+
1V
GATEL NON-
OVERLAP
COMPARATOR
1V
GATEL
DRIVER
IROSC
SYNCHRONOUS RECTIFICATION
DISABLE COMPARATOR
-
+ CURRENT SENSE
AMPLIFIER
CSAOUT
+
-
X33
+
+
DACIN
X
0.75
CALIBRATION
DEBUG
COMPARATOR
-
+
IROSC
PHSOUT
BOOST
GATEH
SW
VCCL
GATEL
PGND
0.2V
CSIN-
CSIN+
Figure 5 Block diagram
Tri-State Gate Drivers
The gate drivers can deliver up to 2A peak current (4A sink current for bottom driver). An adaptive non-overlap
circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot-through current while
minimizing body diode conduction. The non-overlap latch is added to eliminate the error triggering caused by the
switching noise. An enable signal is provided by the control IC to the phase IC without the addition of a dedicated
signal line. The error amplifier output of the control IC drives low in response to any fault condition such as VCCL
under voltage or output overload. The IR3505 Body BrakingTM comparator detects this and drives bottom gate
output low. This tri-state operation prevents negative inductor current and negative output voltage during power-
down.
A synchronous rectification disable comparator is used to detect converter CSIN- pin voltage, which represents
local converter output voltage. If the voltage is below 75% of VDAC and negative current is detected, GATEL drives
low, which disables synchronous rectification and eliminates negative current during power-up.
The gate drivers pull low if the supply voltages are below the normal operating range. An 80kΩ resistor is connected
across the GATEH/GATEL and PGND pins to prevent the GATEH/GATEL voltage from rising due to leakage or
other causes under these conditions.
Page 11 of 19
Sept 26th, 2007
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet IR3505.PDF ] | |
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