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PDF IR3507 Data sheet ( Hoja de datos )
| Número de pieza | IR3507 | |
| Descripción | XPHASE3TM PHASE IC | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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IR3507
DATA SHEET
XPHASE3TM PHASE IC
DESCRIPTION
The IR3507 Phase IC combined with an IR XPhase3TM Control IC provides a full featured and flexible way to
implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides
overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single
phase of a multiphase converter. The XPhase3TM architecture results in a power supply that is smaller, less
expensive, and easier to design while providing higher efficiency than conventional approaches.
FEATURES IR3507 PHASE IC
• Power State Indicator (PSI) interface provides the capability to maximize the efficiency at light loads.
• 7V/2A gate drivers (4A GATEL sink current)
• Converter output voltage up to 5.1 V (Limited to VCCL-1.4V)
• Loss-less inductor current sensing
• Feed-forward voltage mode control
• Integrated boot-strap synchronous PFET
• Only four external components per phase
• 3 wire analog bus connects Control and Phase ICs (VID, Error Amp, IOUT)
• 3 wire digital bus for accurate daisy-chain phase timing control without external components
• Anti-bias circuitry prevents excessive sag in output voltage during PSI de-assertion
• PSI input is ignored during power up
• Debugging function isolates phase IC from the converter
• Self-calibration of PWM ramp, current sense amplifier, and current share amplifier
• Single-wire bidirectional average current sharing
• Small thermally enhanced 20L 4 X 4mm MLPQ package
• RoHS compliant
APPLICATION CIRCUIT
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12V
EAIN
IOUT
PSI
DACIN
PHSIN
PHSOUT
CLKIN
VCCL
Page 1 of 19
1 IOUT
2 PSI
3 DACIN
4 LGND
5 PHSIN
IR3507
SW
GATEH
BOOST
VCCL
NC
15
14
13
12
11
CBST
CVCCL
Figure 1 Application Circuit
RCS
CCS
L
VOUT+
COUT
VOUT-
Jan 09, 2008
1 page  
IR3507
PARAMETER
TEST CONDITION
Body Brake Comparator
Threshold Voltage with EAIN
decreasing
Measure relative to Floor Voltage
Threshold Voltage with EAIN
increasing
Measure relative to Floor Voltage
Hysteresis
Propagation Delay
VCCL = 5V. Measure time from EAIN <
V(DACIN) (200mV overdrive) to GATEL
transition to < 4V.
OVP Comparator
OVP Threshold
Step V(IOUT) up until GATEL drives
high. Compare to V(VCCL)
Propagation Delay
V(VCCL)=5V, Step V(IOUT) up from
V(DACIN) to V(VCCL). Measure time to
V(GATEL)>4V.
Synchronous Rectification Disable Comparator
Threshold Voltage
The ratio of V(CSIN-) / V(DACIN), below
which V(GATEL) is always low.
Negative Current Comparator
Input Offset Voltage
Note 1
Propagation Delay Time
Apply step voltage to V(CSIN+) –
V(CSIN-). Measure time to V(GATEL)<
1V.
Bootstrap Diode
Forward Voltage
I(BOOST) = 30mA, VCCL = 6.8V
Debug Comparator
Threshold Voltage
Compare to V(VCCL)
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VCC Supply Current
VCC Supply Current
VCCL Supply Current
8V 9(VCC) < 10V
10V 9(VCC) 16V
BOOST Supply Current
4.75V 9(BOOST)-V(SW ) 8V
DACIN Bias Current
SW Floating Voltage
MIN
-300
-200
70
40
-1.0
15
66
-16
100
360
-250
1.1
1.1
3.1
0.5
-1.5
0.1
TYP
-200
-100
105
65
-0.8
40
75
0
200
520
-150
4.0
2.0
8.0
1.5
-0.75
0.3
MAX
-110
-10
130
90
-0.4
70
86
16
400
960
-50
6.1
4
12.1
3
1
0.4
UNIT
mV
mV
mV
ns
V
ns
%
mV
ns
mV
mV
mA
mA
mA
mA
µA
V
Note 1: Guaranteed by design, but not tested in production
Note 2: VCCL-0.5V or VCC – 2.5V, whichever is lower
Page 5 of 19
Jan 09, 2008
5 Page 
IR3507
share loop is much slower than that of the voltage loop and the two loops do not interact. For proper current sharing the
output of current sense amplifier should note exceed (VCCL-1.4V) under all operating condition.
IR3507 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3507 is shown in Figure 5, and specific features are discussed in the following sections.
CLKIN
PHSIN
EAIN
VCC
IOUT
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DACIN
PWM LATCH
PWM COMPARATOR
EAIN
-
+
100% DUTY
LATCH
PWMQ D
PWM_CLK CLK Q
Q_100%DUTY
.
.
RMPOUT
PHSIN
VCC
CALIBRATION
DACIN-SHARE_ADJ
PWM RAMP
GENERATOR
DQ
PWM_CLK
CLK Q
RESET
DOMINANT
.
VCCL
PWM RESET
QD
CLK
BODY BRAKING
COMPARATOR
ANTI-BIAS
LATCH
EAIN
DACIN +
-
SHARE_ADJ
DEBUG OFF
(LOW=OPEN)
-
100mV
+
NEGATIVE
200mV
OVP
COMPARATOR
CURRENT
LATCH
VCCL
-
0.8V
QR
+
RESET
S
DOMINANT
SHARE
ADJUST
AMPLIFIER
NEGATIVE CURRENT
COMPARATOR
-
3K +
CALIBRATION
PWMQ
CLK Q
D
Q_100%DUTY
-
+
RMPOUT
200mV
GATEH
DRIVER
GATEH NON-
OVERLAP
GATEH NON-
LATCH
OVERLAP
COMPARATOR
QS
-
SET R
DOMINANT
GATEL NON-
OVERLAP
LATCH
QS
+
1V
GATEL NON-
OVERLAP
COMPARATOR
1V
SET R
DOMINANT
GATEL
DRIVER
SYNCHRONOUS RECTIFICATION
DISABLE COMPARATOR
-
+
CSAOUT
+
CURRENT SENSE
AMPLIFIER
-
X32.5
+
+
IROSCDACIN
X
0.75
CALIBRATION
0.15V
DEBUG
COMPARATOR
LGND
PSI ASSERT
Q D VCCL
CLK
8CLK
QD
CLK
IROSC
VCCL
PHSIN
(CLKIN IF 1-PHASE)
1V
PSI
COMPARATOR
-
+
620mV
550mV
500K
PHSOUT
BOOST
GATEH
SW
VCCL
GATEL
PGND
CSIN-
CSIN+
PSI
Tri-State Gate Drivers
Figure 5: Block diagram
The gate drivers can deliver up to 2A peak current (4A sink current for bottom driver). An adaptive non-overlap
circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot-through current while
minimizing body diode conduction. The non-overlap latch is added to eliminate the error triggering caused by the
switching noise. An enable signal is provided by the control IC to the phase IC without the addition of a dedicated
signal line. The error amplifier output of the control IC drives low in response to any fault condition such as VCCL
under voltage or output overload. The IR3507 Body BrakingTM comparator detects this and drives bottom gate
output low. This tri-state operation prevents negative inductor current and negative output voltage during power-
down.
Page 11 of 19
Jan 09, 2008
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet IR3507.PDF ] | |
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