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PDF 24LC41A Data sheet ( Hoja de datos )
| Número de pieza | 24LC41A | |
| Descripción | 1K/4K 2.5V Dual Mode | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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24LC41A
1K/4K 2.5V Dual Mode, Dual Port I2C™ Serial EEPROM
Features
• Single supply with operation down to 2.5V
• Completely implements DDC1/DDC2 interface
for monitor identification, including recovery to
DDC1
• Improved noise immunity
• Separate high speed 2-wire bus for
microcontroller access to 4K-bit Serial EEPROM
• Low-power CMOS technology
• 2 mA active current typical
• 20 µA standby current typical at 5.5V
• Dual 2-wire serial interface bus, I2C™ compatible
• Hardware write-protect for Microcontroller Access
Port
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes (DDC port) or
16 bytes (4K Port)
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• 1,000,000 erase/write cycles
• Data retention > 40 years
• 8-pin PDIP package
• Available for extended temperature ranges
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
Description
The Microchip Technology Inc. 24LC41A is a dual port
www.DataShee1t24U8.cxom8 and 512 x 8-bit Electrically Erasable PROM
(EEPROM). This device is designed for use in applica-
tions requiring storage and serial transmission of
configuration and control information. Three modes of
operation have been implemented:
• Transmit-only mode for the DDC Monitor Port
• Bidirectional mode for the DDC Monitor Port
• Bidirectional, industry-standard 2-wire bus for the
4K Microcontroller Access Port
Upon power-up, the DDC Monitor Port will be in the
Transmit-only mode, repeatedly sending a serial bit
stream of the entire memory array contents, clocked by
the VCLK pin. A valid high-to-low transition on the
DSCL pin will cause the device to enter the transition
mode, an look for a valid control byte on the I2C bus. If
it detects a valid control byte from the master, it will
switch to Bidirectional mode, with byte selectable read/
write capability of the memory array using DSCL. If no
control byte is received, the device will revert to the
Transmit-only mode after it received 128 consecutive
VCLK Package Type pulses while the DSCL pin is idle.
The 4K-bit microcontroller port is completely indepen-
dent of the DDC port, therefore, it can be accessed
continuously by a microcontroller without interrupting
DDC transmission activity. The 24LC41A is available in
a standard 8-pin PDIP package in both commercial and
industrial temperature ranges.
Package Type
PDIP
DSCL
1
8 DSDA
VCLK 2
7 Vcc
VSS 3
6 MWP
MSDA 4
5 MSCL
Block Diagram
EDID Table
1K-Bit
MSDA
4K-Bit
Serial
EEPROM
DSDA
VCLK
DSCL
MSCL
Pin Function Table
Name
Function
DSCL
DSDA
VCLK
MSCL
MSDA
MWP
VSS
VCC
Serial Clock for DDC Bidirectional mode
(DDC2)
Serial Address and Data I/O(DDC Bus)
Serial Clock for DDC Transmit-only mode
(DDC1)
Serial clock for 4K-bit MCU port
Serial Address and Data I/O for 4K-bit MCU port
Hardware write-protect for Microcontroller
Access Port
Ground
+2.5V to +5.5V power supply
I2C is a trademark of Philips Corporation.
DDC is a trademark of Video Electronics Standards Association.
2003 Microchip Technology Inc.
DS21176D-page 1
1 page  
24LC41A
2.1.3 BIDIRECTIONAL MODE
Before the 24LC41A can be switched into the Bidirec-
tional mode (Figure 2-4), it must enter the transition
mode, which is done by applying a valid high-to-low
transition on the Bidirectional mode Clock (DSCL). As
soon it enters the transition mode, it looks for a control
byte 1010 000X on the I2C™ bus, and starts to count
pulses on VCLK. Any high-to-low transition on the
DSCL line will reset the count. If it sees a pulse count
of 128 on VCLK while the DSCL line is idle, it will revert
back to the Transmit-only mode, and transmit its
contents starting with the Most Significant bit in
address 00h. However, if it detects the control byte on
the I2C bus, (Figure 2-3) it will switch to the in the
Bidirectional mode. Once the device has made the
transition to the Bidirectional mode, the only way to
switch the device back to the Transmit-only mode is to
remove power from the device. The mode transition
process is shown in detail in Figure 2-4.
Once the device has switched into the Bidirectional
mode, the VCLK input is disregarded, with the excep-
tion that a logic high level is required to enable write
capability. This mode supports a two-wire bidirectional
data transmission protocol (I2C). In this protocol, a
device that sends data on the bus is defined to be the
transmitter, and a device that receives data from the
bus is defined to be the receiver. The bus must be
controlled by a master device that generates the
Bidirectional mode Clock (DSCL), controls access to
the bus and generates the Start and Stop conditions,
while the monitor port acts as the slave. Both master
and slave can operate as transmitter or receiver, but
the master device determines which mode is activated.
In the Bidirectional mode, the monitor port only
responds to commands for device 1010 000X.
2.2 Microcontroller Access Port
The Microcontroller Access Port supports a bidirec-
tional 2-wire bus and data transmission protocol. A
device that sends data onto the bus is defined as
transmitter, and a device receiving data as receiver.
The bus has to be controlled by a master device which
generates the serial clock (MSCL), controls the bus
access, and generates the Start and Stop conditions,
while the Microcontroller Access Port works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.
FIGURE 2-3:
SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE
Transmit-only
mode
MODE
SCL
Bidirectional
Transition mode with possibility to return to Transmit-only mode permanently
SDA
S 1 0 1 0 0 0 0 0 ACK
VCLK count = 1 2
VCLK
www.DataSheet4U.com
n0
n < 128
FIGURE 2-4:
MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE
MODE Transmit-only
Bidirectional
TVHZ
SCL
SDA
VCLK count =
VCLK
1234
Recovery to Transmit-only mode
127 128
(MSB of data in 00h)
Bit8
2003 Microchip Technology Inc.
DS21176D-page 5
5 Page 
5.0 ACKNOWLEDGE POLLING
Acknowledge polling can be done for both the DDC
Monitor Port (when in Bidirectional mode) and the
Microcontroller Access Port.
Since the port will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize but
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W=0). If the device is still busy
with the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next Read or
Write command. See Figure 5-1 for the flow diagram.
24LC41A
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
YES
Next
Operation
NO
www.DataSheet4U.com
2003 Microchip Technology Inc.
DS21176D-page 11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet 24LC41A.PDF ] | |
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