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PDF MAX16071 Data sheet ( Hoja de datos )
| Número de pieza | MAX16071 | |
| Descripción | (MAX16070 / MAX16071) Flash-Configurable System Monitors | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-5003; Rev 0; 10/09
12-Channel/8-Channel, Flash-Configurable System
Monitors with Nonvolatile Fault Registers
General Description
The MAX16070/MAX16071 flash-configurable sys-
tem monitors supervise multiple system voltages. The
MAX16070/MAX16071 can also accurately monitor
(Q2.5%) one current channel using a dedicated high-
side current-sense amplifier. The MAX16070 monitors
up to twelve system voltages simultaneously, and the
MAX16071 monitors up to eight supply voltages. These
devices integrate a selectable differential or single-end-
ed analog-to-digital converter (ADC). Device configura-
tion information, including overvoltage and undervoltage
limits and timing settings are stored in nonvolatile flash
memory. During a fault condition, fault flags and channel
voltages can be automatically stored in the nonvolatile
flash memory for later read-back.
The internal 1% accurate 10-bit ADC measures each
input and compares the result to one overvoltage, one
undervoltage, and one early warning limit that can be
configured as either undervoltage or overvoltage. A fault
signal asserts when a monitored voltage falls outside the
set limits. Up to three independent fault output signals
are configurable to assert under various fault conditions.
Because the MAX16070/MAX16071 support a power-
supply voltage of up to 14V, they can be powered
directly from the 12V intermediate bus in many systems.
The MAX16070/MAX16071 include eight/six program-
mable general-purpose inputs/outputs (GPIOs). GPIOs
are flash configurable as dedicated fault outputs, as a
www.DawtaaStchehedt4oUg.cinomput or output, or as a manual reset.
The MAX16070/MAX16071 feature nonvolatile fault mem-
ory for recording information during system shutdown
events. The fault logger records a failure in the internal
flash and sets a lock bit protecting the stored fault data
from accidental erasure. An SMBus™ or a JTAG serial
interface configures the MAX16070/MAX16071. The
MAX16070/MAX16071 are available in a 40-pin, 6mm x
6mm, TQFN package. Both devices are fully specified
from -40NC to +85NC.
Applications
Networking Equipment
Telecom Equipment (Base Stations, Access)
Storage/Raid Systems
Servers
SMBus is a trademark of Intel Corp.
Features
S Operate from 2.8V to 14V
S ±2.5% Current-Monitoring Accuracy
S 1% Accurate 10-Bit ADC Monitors 12/8 Voltage
Inputs
S Single-Ended or Differential ADC for System
Voltage/Current Monitoring
S Integrated High-Side, Current-Sense Amplifier
S 12/8 Monitored Inputs with Overvoltage/
Undervoltage/Early Warning Limit
S Nonvolatile Fault Event Logger
S Two Programmable Fault Outputs and One Reset
Output
S Eight General-Purpose Inputs/Outputs
Configurable as:
Dedicated Fault Outputs
Watchdog Timer Function
Manual Reset
Margin Enable
S SMBus (with Timeout) or JTAG Interface
S Flash Configurable Time Delays and Thresholds
S -40NC to +85NC Operating Temperature Range
Ordering Information
PART
MAX16070ETL+
MAX16071ETL+
TEMP RANGE
-40NC to +85NC
-40NC to +85NC
PIN-PACKAGE
40 TQFN-EP*
40 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configuration and Typical Operating Circuits appear at
end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.)
(Note 1)
PARAMETER
Output Fall Time
Data Hold Time
Pulse Width of Spike Suppressed
JTAG INTERFACE
TDI, TMS, TCK Logic-Low Input
Voltage
TDI, TMS, TCK Logic-High Input
Voltage
TDO Logic-Output Low Voltage
TDO Logic-Output High Voltage
TDI, TMS Pullup Resistors
I/O Capacitance
TCK Clock Period
TCK High/Low Time
TCK to TMS, TDI Setup Time
TCK to TMS, TDI Hold Time
TCK to TDO Delay
TCK to TDO High-Z Delay
SYMBOL
tOF
tHD:DAT
tSP
CONDITIONS
CBUS = 10pF to 400pF
From 50% SCL falling to SDA change
VIL
VIH
VOL
VOH
RPU
CI/O
t1
t2, t3
t4
t5
t6
t7
Input voltage falling
Input voltage rising
ISINK = 3mA
ISOURCE = 200μA
Pullup to DBP
MIN TYP MAX UNITS
250 ns
0.3 0.9 μs
30 ns
0.8
2
0.4
2.4
40 50 60
5
1000
50 500
15
10
500
500
V
V
V
V
kω
pF
ns
ns
ns
ns
ns
ns
Note 1: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at TA =
+25NC and TA = +85NC. Specifications at TA = -40NC are guaranteed by design.
Note 2: For 3.3V VCC applications, connect VCC, DBP, and ABP together. For higher supply applications, connect VCC only to the
supply rail.
www.DaNtaoStehe3e:t4 AUp.cpolimes to RESET, fault, autoretry, sequence delays, and watchdog timeout.
Note 4: Total unadjusted error is a combination of gain, offset, and quantization error.
_______________________________________________________________________________________ 5
5 Page 
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Detailed Description
The MAX16070 monitors up to twelve system power sup-
plies and the MAX16071 can monitor up to eight system
power supplies. After boot-up, if EN is high and the soft-
ware enable bit is set to ‘1,’ monitoring begins based on
the configuration stored in flash. An internal multiplexer
cycles through each MON_ input. At each multiplexer
stop, the 10-bit ADC converts the monitored analog volt-
age to a digital result and stores the result in a register.
Each time a conversion cycle (50Fs, max) completes,
internal logic circuitry compares the conversion results
to the overvoltage and undervoltage thresholds stored in
memory. When a result violates a programmed threshold,
the conversion can be configured to generate a fault.
GPIO_ can be programmed to assert on combinations
of faults. Additionally, faults can be configured to shut off
the system and trigger the nonvolatile fault logger, which
writes all fault information automatically to the flash and
write-protects the data to prevent accidental erasure.
The MAX16070/MAX16071 contain both SMBus and
JTAG serial interfaces for accessing registers and flash.
Use only one interface at any given time. For more infor-
mation on how to access the internal memory through
these interfaces, see the SMBus-Compatible Interface
and JTAG Serial Interface sections. The memory map
is divided into three pages with access controlled by
special SMBus and JTAG commands.
The factory-default values at POR (power-on reset) for all
www.DaRtaASMheeret4gUis.cteomrs are ‘0’s. POR occurs when VCC reaches
the undervoltage-lockout threshold (UVLO) of 2.8V (max).
At POR, the device begins a boot-up sequence. During
the boot-up sequence, all monitored inputs are masked
from initiating faults and flash contents are copied to
the respective register locations. During boot-up, the
MAX16070/MAX16071 are not accessible through the
serial interface. The boot-up sequence takes up to
150Fs, after which the device is ready for normal opera-
tion. RESET is asserted low up to the boot-up phase and
remains asserted for its programmed timeout period once
sequencing is completed and all monitored channels
are within their respective thresholds. Up to the boot-up
phase, the GPIO_s are high impedance.
Power
Apply 2.8V to 14V to VCC to power the MAX16070/
MAX16071. Bypass VCC to ground with a 10FF capaci-
tor. Two internal voltage regulators, ABP and DBP,
supply power to the analog and digital circuitry within
the device. For operation at 3.6V or lower, disable the
regulators by connecting ABP and DBP to VCC.
ABP is a 3.0V (typ) voltage regulator that powers the inter-
nal analog circuitry. Bypass ABP to GND with a 1FF ceram-
ic capacitor installed as close to the device as possible.
DBP is an internal 3.0V (typ) voltage regulator. DBP pow-
ers flash and digital circuitry. All push-pull outputs refer to
DBP. Bypass the DBP output to GND with a 1FF ceramic
capacitor installed as close as possible to the device.
Do not power external circuitry from ABP or DBP.
Enable
To enable monitoring, the voltage at EN must be above
1.4V and the software enable bit in r73h[0] must be set
to ‘1.’ To power down and disable monitoring, either pull
EN below 1.35V or set the Software Enable bit to ‘0.’
See Table 1 for the software enable bit configurations.
Connect EN to ABP if not used.
Table 1. Software Enable Configurations
REGISTER
ADDRESS
73h
FLASH
ADDRESS
273h
BIT RANGE
[0]
[1]
[2]
[3]
DESCRIPTION
Software enable
Reserved
1 = Margin mode enabled
Early warning threshold select
0 = Early warning is undervoltage
1 = Early warning is overvoltage
Independent watchdog mode enable
[4] 1 = Watchdog timer is independent of sequencer
0 = Watchdog timer boots after sequence completes
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MAX16071.PDF ] | |
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