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PDF SEPS225 Data sheet ( Hoja de datos )
| Número de pieza | SEPS225 | |
| Descripción | 262K Colors PM-OLED Display Driver and Controller | |
| Fabricantes | SYNCOAM | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SEPS225 (archivo pdf) en la parte inferior de esta página. Total 44 Páginas | ||
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No Preview Available !
Synergetic Combination of ASIC & Memory
SYNCOAM Co., Ltd
Version: 0.8
Date: December 07, 2005
SEPS225
128 x 128 Dots, 262K Colors PM‐OLED Display Driver and Controller
1. Product Preview
▪ 262k colors OLED single chip display driver IC
▪ Data Interface
‐ Parallel interface : 68/80series MPU(8/16/18‐bit)
‐ Serial interface : SPI 4‐wire interface
‐ RGB interface : 18/16/6‐bit interface
▪ Driver Output
‐ 128× RGB columns(384), 128 rows
▪ Display RAM Capacity
‐ 128 × 18(RGB) × 128 = 294,912 bits
▪ Various Instructions Set
‐ Power save mode
‐ Reduced current driving available
‐ Window mode
‐ Partial display : programmable panel display size
‐ Vertical scroll & Horizontal panning
▪ OLED Column Drive
‐ Driving current control : 8‐bit, 0uA ~ 255uA by 1uA step control
‐ Pre_charge current control : 8‐bit, 0uA ~ 2040uA by 8uA step control
‐ Pre_charge time control : programmable pre_charge time(0clock ~ 14clocks) based on
internal oscillator clock
▪ OLED Row Drive
www.DataS heet4U.‐c Comurrent sink : Max 100mA
▪ Internal Oscillator Circuit
‐ Internal / External clock selectable
‐ Frame rate : 90 frames/sec( 75.0 ~ 150.0 frames/sec adjustable)
▪ Supply Voltage
‐ VDD : 2.4 ~ 3.3V
‐ VDDH : 8.0 ~ 18.0V
▪ Package : Au Bumped
▪ Ordering information
SEPS225T0A TCP Package
SEPS225F0A COF Package
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1 page  
SYNCOAM Co., Ltd. SEPS225 Version: 0.8
1) 18‐bit Bus Interface(Index 16h)
DFM1
DFM0
TRI
Operation
0 0 x
18‐bit bus operation
Index/Command Write
DDRAM Read/Write
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5 Page 
SYNCOAM Co., Ltd. SEPS225 Version: 0.8
6) RGB Interface
When the RGB_IF register bit0 is set to “0”, SEPS225 enters into the RGB interface mode and DDRAM write
cycle is synchronized by DOTCLK.
18‐bit RGB interface
The 18‐bit RGB interface is selected by setting RIM[1:0] bits to “00”. DDRAM write operation is
Synchronized with DOTCLK and ENABLE. Display data are transmitted to DDRAM in synchronization
with 18‐bit RGB data bus(DB[17:0]) and the data enable(ENABLE).
DDRAM Write
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11 Page | ||
| Páginas | Total 44 Páginas | |
| PDF Descargar | [ Datasheet SEPS225.PDF ] | |
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