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Número de pieza | ICS91305I | |
Descripción | High Performance Communication Buffer | |
Fabricantes | Integrated Circuit Systems | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de ICS91305I (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
No Preview Available ! Integrated
Circuit
Systems, Inc.
ICS91305I
High Performance Communication Buffer
General Description
The ICS91305I is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology
to align, in both phase and frequency, the REF input with
the CLKOUT signal. It is designed to distribute high speed
clocks in communication systems operating at speeds
from 10 to 133 MHz.
ICS91305I is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to
the input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
The ICS91305I comes in an eight pin 150 mil SOIC
package. It has five output clocks. In the absence of REF
input, will be in the power down mode. In this mode, the
PLL is turned off and the output buffers are pulled low.
Power down mode provides the lowest power consumption
for a standby condition.
Features
• Zero input - output delay
• Frequency range 10 - 133 MHz (3.3V)
• 5V tolerant input REF
• High loop filter bandwidth ideal for Spread
Spectrum applications.
• Less than 200 ps Jitter between outputs
• Skew controlled outputs
• Skew less than 250 ps between outputs
• Available in 8 pin 150 mil SOIC & 173 mil
TSSOP packages
• 3.3V ±10% operation
• Supports industrial temperature range -40°C to
85°C
Pin Configuration
Block Diagram
REF 1
CLK2 2
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CLK1 3
GND 4
8 CLKOUT
7 CLK4
6 VDD
5 CLK3
8 pin SOIC & TSSOP
0691F—06/03/05
1 page ICS91305I
Output to Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded
than CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause
them to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded Equally
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REF input and CLK(1-4)
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLK(1_4)
outputs loaded equally, with
CLKOUT loaded Less.
0691F—06/03/05
Timing diagrams with different loading configurations
5
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet ICS91305I.PDF ] |
Número de pieza | Descripción | Fabricantes |
ICS91305 | High Performance Communication Buffer | Integrated Circuit Systems |
ICS91305I | High Performance Communication Buffer | Integrated Circuit Systems |
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