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PDF L64704 Data sheet ( Hoja de datos )
| Número de pieza | L64704 | |
| Descripción | Satellite Decoder Technical Manual 5/97 | |
| Fabricantes | LSI Ligic | |
| Logotipo |  |
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L64704 Satellite Decoder
Technical Manual
May 1997
www.DataSheet4U.com
Order Number I14010.A
1 page  
May 1997
3.6.24
3.6.25
3.6.26
3.6.27
3.6.28
3.6.29
3.6.30
3.6.31
Group 4, APR 27 Carrier Lock Detector Threshold 3-43
Group 4, APR 28 Carrier Synchronizer Sweep
Rate
3-44
Group 4, APR 29, 30 Carrier Synchronizer Sweep
Upper Limit
3-44
Group 4, APR 31, 32 Carrier Synchronizer Sweep
Lower Limit
3-45
Group 4, APR 33 Carrier Loop Configuration
Register
3-45
Group 4, APR 34 Set to 0
3-48
Group 4, APR 35 Decoder Configuration Register 3-49
Group 4, APR 36 External Output Control Bits
and Reset Register
3-50
Chapter 4
www.DataSheet4U.com
Channel Interfaces and Data Control
4.1 Data Control and Clocking Schemes
4.2 Channel Data Input Interface
4.3 Channel Data Output Interface
4.4 PLL Clock Generation
4.5 Data Path Output Configurations
4.5.1 Descrambler Output
4.5.2 Synchronization Stage 3 Output
4.5.3 Reed-Solomon Decoder Output
4.5.4 Deinterleaver Output
4.5.5 Synchronization Stage 2 Output
4.5.6 Viterbi Decoder Output
4.5.7 Viterbi Depuncture/Synchronization Output
4.5.8 QPSK Demodulator Output
4-2
4-4
4-5
4-5
4-12
4-13
4-15
4-15
4-16
4-17
4-17
4-18
4-19
Chapter 5
Demodulator Module Functional Description
5.1 Overview
5.2 DC Offset Compensation and Coupling to ADC Output
5.3 Decimation Filters
5.4 Matched Filter
5.5 Channel Clock Recovery
5.5.1 Input Decimation
5.5.2 Clock Acquisition and Tracking Modes
5-1
5-3
5-3
5-4
5-4
5-5
5-5
Contents
Rev. letter
Copyright © 1995, 1996, 1997 by LSI Logic Corporation. All rights reserved.
v
5 Page 
May 1997
www.DataSheet4U.com
5.4
5.5
6.1
7.1
7.2
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
B.1
B.2
B.3
B.4
B.5
B.6
B.7
B.8
B.9
B.10
C.1
C.2
C.3
Example of Data Rates for Narrow SAW Filter
PWR_BW as a Function of Symbol Rate
Stage 2 Synchronization Values
Puncture Patterns for Various Code Rates
Viterbi Threshold Values
L64704 Absolute Maximum Rating (Referenced to VSS)
L64704 Recommended Operating Conditions
L64704 Capacitance
L64704 DC Characteristics
L64704 Pin Description Summary
L64704 AC Timing Parameters
L64704 Ordering Information
Alphabetical Pin List for the 100-pin PQFP
QPSK Demodulator Loop Registers
PWR_LVL Register Setting
QPSK Demodulator Loop Registers
ωn for Fixed Rate Operation (Damping = 1)
Group 4 Decoder Register Map
Group 4 Decoder Registers Actual Configuration
Typical Clock and Carrier VCO Gains
CAR_PED Output Pins
Group 4 Register Map
Group 4 Actual Configuration
Component Values for the Circuit Shown in Figure C.2
Component Values for the Circuit Shown in Figure C.3
Component Values for the Circuit Shown in Figure C.4
5-10
5-23
6-9
7-4
7-7
8-2
8-2
8-2
8-3
8-4
8-8
8-10
8-10
B-2
B-4
B-6
B-11
B-14
B-15
B-16
B-17
B-18
B-19
C-3
C-4
C-5
Contents
Rev. letter
Copyright © 1995, 1996, 1997 by LSI Logic Corporation. All rights reserved.
xi
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet L64704.PDF ] | |
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