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PDF ICS8430B-71L Data sheet ( Hoja de datos )
| Número de pieza | ICS8430B-71L | |
| Descripción | CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8430B-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS8430B-71 is a general purpose, dual out-
ICS put Crystal/LVCMOS-to-3.3V Differential LVPECL
HiPerClockS™ High Frequency Synthesizer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8430B-71 has a se-
lectable crystal oscillator interface or LVCMOS TEST_CLK.
The VCO operates at a frequency range of 250MHz to
700MHz. With the output configured to divide the VCO
frequency by 2, output frequency steps as small as 2MHz
can be achieved using a 16MHz crystal or test clock. Output
frequencies up to 700MHz can be programmed using the
serial or parallel interfaces to the configuration logic. The low
jitter and frequency range of the ICS8430B-71 make it an
ideal clock generator for most clock tree applications.
FEATURES
• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS TEST_CLK
• Output frequency up to 700MHz
• Crystal input frequency range: 12MHz to 27MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 9ps (maximum)
• Cycle-to-cycle jitter: 25ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Replaces 8430-71
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
XTAL_SEL
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0
XTAL_IN
XTAL_OUT
OSC 1
÷ 16
PLL
PHASE DETECTOR
32 31 30 29 28 27 26 25
M5 1
M6 2
M7 3
M8 4
N0 5
N1 6
N2 7
VEE 8
ICS8430B-71
24 XTAL_OUT
23 TEST_CLK
22 XTAL_SEL
2 1 VCCA
20 S_LOAD
19 S_DATA
18 S_CLOCK
17 MR
9 10 11 12 13 14 15 16
MR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
VCO
0
÷N
÷M 1
÷2
CONFIGURATION
INTERFACE
LOGIC
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
M0:M8
N0:N2
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8430BY-71
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 20, 2005
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8430B-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Inputs, VI
Outputs, IO
Continuous Current
Surge Current
Package Thermal Impedance, θJA
Storage Temperature, T
STG
4.6V
-0.5V to VCC + 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
VCC
VCCA
VCCO
IEE
ICCA
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.135
3.135
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
140
15
Units
V
V
V
mA
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions Minimum Typical Maximum Units
TEST_CLK; NOTE 1
VIH
Input
VCO_SEL, S_LOAD, S_DATA,
High Voltage S_CLOCK, nP_LOAD, MR,
M0:M8, N0:N2, XTAL_SEL
VIL Input Low Voltage
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M0-M7, N0, N1, MR, nP_LOAD,
IIH
Input
S_CLOCK, S_DATA, S_LOAD
High Current M8, N2, XTAL_SEL, VCO_SEL
TEST_CLK
M0-M7, N0, N1, MR, nP_LOAD,
IIL
Input
S_CLOCK, S_DATA, S_LOAD
Low Current TEST_CLK, M8, N2,
XTAL_SEL, VCO_SEL
VOH
Output
High Voltage
TEST; NOTE 2
VOL
Output
Low Voltage
TEST; NOTE 2
NOTE 1: Characterized with 1ns input edge rate.
NOTE 2: Outputs terminated with 50Ω to VCCO/2.
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V,
VIN = 0V
VCC = 3.465V,
VIN = 0V
2.35
2
-0.3
-5
-150
2.6
VCC + 0.3
VCC + 0.3
0.8
150
5
200
V
V
V
µA
µA
µA
µA
µA
V
0.5 V
TABLE
4C.
LVPECL
DC
CHARACTERISTICS,
V
CC
=
V
CCA
=
V
CCO
=
3.3V±5%,
TA
=
0°C
TO
70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VOH Output High Voltage; NOTE 1
VCC - 1.4
VOL Output Low Voltage; NOTE 1
VCC - 2.0
VSWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"3.3V Output Load Test Circuit" figure.
VCC - 0.9
VCC - 1.7
1.0
V
V
V
8430BY-71
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 20, 2005
5
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8430B-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads.This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the VCCA as possible.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system fail-
ure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ring-
ing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be re-
stricted by the available space on the board and the component
location.While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
• The traces with 50Ω transmission lines TL1 and TL2
at FOUT and nFOUT should have equal delay and run
adjacent to each other. Avoid sharp angles on the clock
trace. Sharp angle turns cause the characteristic
impedance to change on the transmission lines.
• Keep the clock trace on the same layer. Whenever pos-
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
• Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible.
Other termination schemes can also be used but are not
shown in this example.
CRYSTAL
The crystal X1 should be located as close as possible to the
pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length be-
tween the X1 and U1 should be kept to a minimum to avoid
unwanted parasitic inductance and capacitance. Other signal
traces should not be routed near the crystal traces.
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C1
U1
PIN 1
C2
X1
C11
R7
C16
VCCA
GND
VCC
VIA
Close to the input
pins of the
receiver
8430BY-71
C15
C14
TL1 R1
R2
TL1N
TL1, TL21N are 50 Ohm
traces and equal length
R3
R4
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8430B-71
www.icst.com/products/hiperclocks.html
11
REV. A SEPTEMBER 20, 2005
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS8430B-71L.PDF ] | |
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