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PDF 71C17403C Data sheet ( Hoja de datos )

Número de pieza 71C17403C
Descripción GM71C17403C
Fabricantes Hynix Semiconductor 
Logotipo Hynix Semiconductor Logotipo



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No Preview Available ! 71C17403C Hoja de datos, Descripción, Manual

GM71C(S)17403C/CL
4,194,304 WORDS x 4 BIT
CMOS DYNAMIC RAM
Description
The GM71C(S)17403C/CL is the new
generation dynamic RAM organized 4,194,304
words x 4 bit. GM71C(S)17403C/CL has
realized higher density, higher performance and
various functions by utilizing advanced CMOS
process technology. The GM71C(S)17403C/CL
offers Extended Data Out (EDO) Mode as a
high speed access mode. Multiplexed address
inputs permit the GM71C(S)17403C/CL to be
packaged in a standard 300 mil 24(26) pin SOJ
and a standard 300mil 24(26) pin plastic TSOP
II. The package size provides high system bit
densities and is compatible with widely
available automated testing and insertion
equipment. System oriented features include
single power supply 5V+/-10% tolerance, direct
interfacing capability with high performance
logic families such as Schottky TTL.
Pin Configuration
24(26) SOJ
www.DataSheet4U.com
VCC 1
I/O1 2
I/O2 3
WE 4
RAS 5
NC 6
26 VSS
25 I/O4
24 I/O3
23 CAS
22 OE
21 A9
Features
* 4,194,304 Words x 4 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time
(Unit: ns)
t t t tRAC CAC
RC HPC
GM71C(S)17403C/CL-5 50 13 84 20
GM71C(S)17403C/CL-6 60 15 104 25
GM71C(S)17403C/CL-7 70 18 124 30
* Low Power
Active : 660/605/550mW (MAX)
Standby : 11mW (CMOS level : MAX)
: 0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Battery Backup Operation (L-version)
* Test Function : 16bit parallel test mode
24(26) TSOP II
VCC 1
I/O1 2
I/O2 3
WE 4
RAS 5
A11 6
26 VSS
25 I/O4
24 I/O3
23 CAS
22 OE
21 A9
A10 8
A0 9
A1 10
A2 11
A3 12
VCC 13
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
A10 8
A0 9
A1 10
A2 11
A3 12
VCC 13
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
(Top View)
Rev 0.1 / Apr’01

1 page




71C17403C pdf
Read Cycle
Symbol
Parameter
tRAC
tCAC
tAA
tOAC
tRCS
tRCH
tRRH
tRAL
tCAL
tCLZ
tOH
tOHO
tOFF
tOEZ
tCDD
tRCHR
tOHR
www.DataSheet4U.ctoOFmR
tWEZ
tWDD
Access Time from RAS
Access Time from CAS
Access Time from Address
Access Time from OE
Read Command Setup Time
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
Column Address to CAS Lead Time
CAS to Output in Low-Z
Output Data Hold Time
Output Data Hold Time from OE
Output Buffer Turn-off Time
Output Buffer Turn-off Time to OE
CAS to DIN Delay Time
Read Command Hold Time from RAS
Output Data hold Time from RAS
Output Buffer turn off to RAS
Output Buffer turn off to WE
WE to DIN Delay Time
tRDD RAS to DIN Delay Time
GM71C(S)17403C/CL
GM71C(S)17403 GM71C(S)17403 GM71C(S)17403
C/CL-5
C/CL-6
C/CL-7
Unit
Min Max Min Max Min Max
- 50 - 60 - 70 ns
Note
8,9,19
- 13 - 15 - 18 ns 9,10,17,19
- 25 - 30 - 35 ns 9,11,17,19
- 13 - 15 - 18 ns
9
0-
0-
0-
0-
0-
0-
ns
ns
12
5- 5- 5-
25 - 30 - 35 -
ns
ns
12
15 - 18 - 23 - ns
0 - 0 - 0 - ns
3 - 3 - 3 - ns
3 - 3 - 3 - ns
- 13 - 15 - 15 ns
13
- 13 - 15 - 15 ns 13,23
13 - 15 - 18 - ns
5
50 - 60 - 70 - ns
3 - 3 - 3 - ns
- 13 - 15 - 15 ns 13,23
- 13 - 15 - 15 ns
13
13 - 15 - 18 - ns
13 - 15 - 18 - ns
Rev 0.1 / Apr’01

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