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PDF XR16C864 Data sheet ( Hoja de datos )
| Número de pieza | XR16C864 | |
| Descripción | 2.97V TO 5.5V QUAD UART | |
| Fabricantes | Exar Corporation | |
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XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
APRIL 2004
GENERAL DESCRIPTION
FEATURES
REV. 2.0.1
The XR16C8641 (864) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) each with 128 bytes of transmit and receive
FIFOs, transmit and receive FIFO counters and
trigger levels, automatic hardware and software flow
control, automatic RS-485 half-duplex direction
control and data rates of up to 2 Mbps. Each UART
has a set of registers that provide the user with
operating status and control, receiver error
indications, and modem serial interface controls.
System interrupts may be tailored to meet design
requirements. An internal loopback capability allows
onboard diagnostics. The 864 is available in the 100-
pin QFP package. The XR16C864 offers faster
channel status access by providing separate outputs
for TXRDY and RXRDY, offer separate Infrared TX
outputs and a separate clock input for channel C
(CHCCLK). The XR16C864 is compatible with the
industry standard ST16C554/554D, ST16C654/654D
and XR16C854/854D.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787.
Added feature in devices with top mark date code of
"F2 YYWW" and newer:
s 5 volt tolerant inputs
• 2.97 to 5.5 Volt Operation
• Pin-to-pin compatible with the industry standard
ST16C554 and ST16C654 and TI’s TL16C554N
and TL16C754BFN
• Intel or Motorola Data Bus Interface select
• Four independent UART channels
s Register Set Compatible to 16C550
s Data rates of up to 2 Mbps
s Transmit and Receive FIFOs of 128 bytes
s Programmable TX and RX FIFO Trigger Levels
s Transmit and Receive FIFO Level Counters
s Automatic Hardware (RTS/CTS) Flow Control
s Selectable Auto RTS Flow Control Hysteresis
s Automatic Software (Xon/Xoff) Flow Control
s Wireless Infrared (IrDA 1.0) Encoder/Decoder
• Sleep Mode (200 uA typical)
• Crystal oscillator or external clock input
APPLICATIONS
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FIGURE 1. XR16C864 BLOCK DIAGRAM
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
A2:A0
D7:D0
IOR#
IO W #
CS# A-D
INT A-D
TXRDY# A-D
RXRDY# A-D
Reset
16/68#
INTSEL
CLKSEL
CHCCLK
TC
AEN
DACK A-D
TXDRQ# A-D
RXDRQ# A-D
XTAL1
XTAL2
BCLK A-D
Intel or
M o to ro la
Data Bus
Interface
Direct
Memory
Access
Crystal Osc/Buffer
5V tolerant inputs (except XTAL1)
UART Channel A
UART
Regs
BRG
128 Byte TX FIFO
TX & RX
IR
ENDEC
128 Byte RX FIFO
UART Channel B
(same as Channel A)
UART Channel C
(same as Channel A)
UART Channel D
(same as Channel A)
2.97V to 5.5V VCC
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#, OP2A#,
OP1A#/RS-485
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#, OP2B#,
OP1B#/RS-485
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#, OP2C#,
OP1C#/RS-485
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#, OP2D#,
OP1D#/RS-485
854 BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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REV. 2.0.1
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
Pin Description
NAME
100-QFP
TYPE
PIN #
DESCRIPTION
TC 54 I Direct Memory Access Terminal Count. A high pulse terminates a Direct Memory Access
transaction. If Direct Memory Access is not used, this input should be connected to GND.
AEN
27 I Address Enable for Direct Memory Access. A high at this input indicates a valid Direct
Memory Access cycle. See DACK pin descriptions below for Direct Memory Access cycle
description. If Direct Memory Access is not used, this input should be connected to GND.
DACKA 4 I Direct Memory Access Acknowledge. Direct Memory Access cycle will start processing
DACKB
DACKC
DACKD
26
55
77
when CPU/Host sets this input low and AEN high. All writes will be to the TX FIFO and all
reads will be from the RX FIFO. A0-A2 and CS# A-D will be ignored. If Direct Memory
Access is not used, these inputs should be connected to VCC.
TXDRQA
TXDRQB
TXDRQC
TXDRQD
5
25
56
81
O Transmit Direct Memory Access Request. A transmit empty request is indicated by a high
level on TXDRQ. The TXDRQ line is held high until either TC pulses or the TX FIFO is
filled above its trigger level. Transmit Direct Memory Access Request is enabled by set-
ting EMSR register bit-2 = 1. If Direct Memory Access is not used, leave these outputs
unconnected.
RXDRQA
RXDRQB
RXDRQC
RXDRQD
100
31
50
82
O Receive Direct Memory Access Request. A Receive ready request is indicated by a high
level on RXDRQ. The RXDRQ line is held high until either TC pulses or the RX FIFO is
emptied. Receive Direct Memory Access Request is enabled by setting EMSR register
bit-3 = 1. If Direct Memory Access is not used, leave these outputs unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
TXB
TXC
TXD
14 O UART channels A-D Transmit Data and infrared transmit data. Standard transmit and
16 receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic
65 1 during reset, or idle (no data). Infrared IrDA transmit and receive interface is enabled
when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared
67 encoder/decoder interface is a logic 0.
IRTXA
6 O UART channels A-D Infrared Transmit Data. The inactive state (no data) for the Infrared
IRTXB
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24
57
encoder/decoder interface is a logic 0. Regardless of the logic state of MCR bit-6, this pin
will be operating in the Infrared mode.
IRTXD
75
RXA
RXB
RXC
RXD
97 I UART channels A-D Receive Data or infrared receive data. Normal receive data input
34 must idle at logic 1 condition. The infrared receiver pulses typically idles at logic 0 but can
47 be inverted by software control prior going in to the decoder, see FCTR[2].
85
RTSA#
RTSB#
RTSC#
RTSD#
11 O UART channels A-D Request-to-Send (active low) or general purpose output. This output
19 must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1], FCTR[1:0],
62 EMSR[5:4] and IER[6]. Also see Figure 10. If these outputs are not used, leave them
70 unconnected.
CTSA# 8 I UART channels A-D Clear-to-Send (active low) or general purpose input. It can be used
CTSB#
CTSC#
22
59
for auto CTS flow control, see EFR[7], and IER[7]. Also see Figure 10. These inputs
should be connected to VCC when not used.
CTSD#
73
5
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REV. 2.0.1
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
TABLE 2: CHANNEL A-D SELECT IN 68 MODE
CS# A4 A3
1 N/A N/A
000
001
010
011
FUNCTION
UART de-selected
Channel A selected
Channel B selected
Channel C selected
Channel D selected
2.6 Channels A-D Internal Registers
Each UART channel in the 864 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the 864 offers enhanced feature registers (EMSR, FLVL,
EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware flow control,
Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO trigger
level control, and FIFO level counters. All the register functions are discussed in full detail later in “Section 3.0,
UART INTERNAL REGISTERS” on page 22.
2.7 INT Ouputs for Channels A-D
The interrupt outputs change according to the operating mode and enhanced features setup. Table 3 and 4
summarize the operating behavior for the transmitter and receiver. Also see Figure 19 through 23.
TABLE 3: INT PINS OPERATION FOR TRANSMITTER FOR CHANNELS A-D
FCTR
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FCR BIT-0 = 0
(FIFO DISABLED)
INT Pin
0 0 = a byte in THR
1 = THR empty
INT Pin
1 0 = a byte in THR
1 = transmitter empty
FCR BIT-0 = 1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO
empty
0 = FIFO above trigger level
1 = FIFO below trigger level or
transmitter empty
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO
empty
0 = FIFO above trigger level
1 = FIFO below trigger level or
transmitter empty
TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin 0 = no data
1 = 1 byte
FCR Bit-3 = 0
(DMA Mode Disabled)
0 = FIFO below trigger level
1 = FIFO above trigger level
FCR Bit-3 = 1
(DMA Mode Enabled)
0 = FIFO below trigger level
1 = FIFO above trigger level
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| PDF Descargar | [ Datasheet XR16C864.PDF ] | |
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