DataSheet.es    


PDF ICS8516 Data sheet ( Hoja de datos )

Número de pieza ICS8516
Descripción 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



Hay una vista previa y un enlace de descarga de ICS8516 (archivo pdf) en la parte inferior de esta página.


Total 15 Páginas

No Preview Available ! ICS8516 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
GENERAL DESCRIPTION
FEATURES
ICS
HiPerClockS™
The ICS8516 is a low skew, high performance Sixteen differential LVDS outputs
1-to-16 Differential-to-LVDS Clock Distribution
Chip and a member of the HiPerClockS ™
family of High Performance Clock Solutions from
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
ICS. The ICS8516 CLK, nCLK pair can accept
any differential input levels and translates them to 3.3V LVDS
output levels. Utilizing Low Voltage Differential Signaling
(LVDS), the ICS8516 provides a low power, low noise, point-
Maximum output frequency: 700MHz
Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
to-point solution for distributing clock signals over controlled Translates any single-ended input signal to LVDS
impedances of 100Ω.
with resistor bias on nCLK input
Dual output enable inputs allow the ICS8516 to be used in a Multiple output enable inputs for disabling unused
1-to-16 or 1-to-8 input/output mode.
outputs in reduced fanout applications
Guaranteed output and part-to-part skew specifications make
the ICS8516 ideal for those applications demanding well
defined performance and repeatability.
LVDS compatible
Output skew: 90ps (maximum)
Part-to-part skew: 500ps (maximum)
Propagation delay: 2.4ns (maximum)
Additive phase jitter, RMS: 148fs (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
www.DataSheet4U.com
CLK
nCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
8516FY
OE1
OE2
PIN ASSIGNMENT
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
VDD
nQ5
Q5
nQ4
Q4
VDD
GND
nQ3
Q3
nQ2
Q2
VDD
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6
7
ICS8516
31
30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
VDD
nQ10
Q10
nQ11
Q11
VDD
GND
nQ12
Q12
nQ13
Q13
VDD
48-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. B FEBRUARY 21, 2006

1 page




ICS8516 pdf
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VOD
Δ VOD
VOS
Δ VOS
IOZ
IOFF
IOSD
IOS/IOSB
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
High Impedance Leakage Current
Power Off Leakage
Differential Output Short Circuit Current
Output Short Circuit Current
Minimum
250
1.125
-10
-1
Typical
400
1.4
Maximum
600
50
1.6
50
+10
+1
-5.5
-12
Units
mV
mV
V
mV
µA
µA
mA
mA
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
tPD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
700
1.6 2.0
2.4
90
tsk(pp) Part-to-Part Skew; NOTE 3, 4
500
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Integration Range:
12kHz - 20MHz
148
t /t Output Rise/Fall Time
RF
odc Output Duty Cycle
20% to 80%
100 550
45 50 55
tPZL, tPZH Output Enable Time; NOTE 5
tPLZ, tPHZ Output Disable Time; NOTE 5
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
www.DatNaSOhTeEet24U: D.ceofmined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
5
5
Units
MHz
ns
ps
ps
fs
ps
%
ns
ns
8516FY
www.icst.com/products/hiperclocks.html
5
REV. B FEBRUARY 21, 2006

5 Page





ICS8516 arduino
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers re-
quire a matched load termination of 100Ω across near the
receiver input. For a multiple LVDS outputs buffer, if only par-
tial outputs are used, it is recommended to terminate the un-
used outputs.
3.3V
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
R1
100
3.3V
CLK
nCLK HiPerClockS
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example of ICS8516. In this ex-
ample, the input is driven by an LVDS driver. For LVDS buffer,
it is recommended to terminate the unused outputs for better
signal integrity. The decoupling capacitors should be physi-
cally located near the power pin.
www.DataSheet4U.com
VDD=3.3V
Zo = 50 Ohm
R16
100
Zo = 50 Ohm
+
-
LVDS_input
U1
8516
LVDS_Driver
Zo = 50 Ohm
R17
100
Zo = 50 Ohm
13
14
15
16
nQ1
Q1
nQ0
17 Q0
18
19
20
GND
nCLK
CLK
21
22
23
24
GND
Q15
nQ15
Q14
nQ14
Q6
nQ6
Q7
nQ7
GND
OE1
OE2
GND
nQ8
Q8
nQ9
Q9
48
47
46
45
44
43
42
41
40
39
38
37
Zo = 50 Ohm
R10
100
Zo = 50 Ohm
+
-
LVDS_input
8516FY
(U1-1)
(U1-6)
VDD=3.3V
(U1-12)
(U1-25)
(U1-31)
(U1-36)
C1 C2
0.1u
0.1u
C3 C4 C5 C6
0.1u
0.1u
0.1u
0.1u
Decoupling capacitors located near the power pins
Zo = 50 Ohm
R1
100
Zo = 50 Ohm
+
-
LVDS_input
FIGURE 4. ICS8516 LVDS BUFFER SCHEMATIC EXAMPLE
www.icst.com/products/hiperclocks.html
11
REV. B FEBRUARY 21, 2006

11 Page







PáginasTotal 15 Páginas
PDF Descargar[ Datasheet ICS8516.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
ICS85105IDIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFERIntegrated Device Technology
Integrated Device Technology
ICS8512061ISINGLE CHANNEL 0.7V DIFFERENTIALTO-LVTTL TRANSCEIVERIntegrated Device Technology
Integrated Device Technology
ICS85161-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIPIntegrated Circuit Systems
Integrated Circuit Systems
ICS8516I1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIPIntegrated Circuit Systems
Integrated Circuit Systems

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar