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PDF ICS85105I Data sheet ( Hoja de datos )
| Número de pieza | ICS85105I | |
| Descripción | DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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LOW SKEW, 1-TO-5, DIFFERENTIAL/
LVCMOS-TO-0.7V HCSL FANOUT BUFFER
ICS85105I
GENERAL DESCRIPTION
The ICS85105I is a low skew, high performance 1-
ICS to-5 Differential-to-0.7V HCSL Fanout Buffer and
HiPerClockS™ a member of the HiPerClockS™ family of High
Perfor mance Clock Solutions from IDT. The
ICS85105I has two selectable clock inputs. The
CLK0, nCLK0 pair can accept most standard differential
input levels. The single-ended CLK1 can accept LVCMOS or
LVTTL input levels. The clock enable is internally synchronized
to eliminate runt clock pulses on the outputs during asynchro-
nous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make
the ICS85105I ideal for those applications demanding well
defined performance and repeatability.
FEATURES
• Five 0.7V differential HCSL outputs
• Selectable differential CLK0, nCLK0 or LVCMOS inputs
• CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 500MHz
• Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
• Output skew: 100ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Propagation delay: 3.2ns (maximuml)
• Additive phase jitter, RMS: 0.24ps (typical)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
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CLK0 Pulldown
nCLK0 Pullup/Pulldown
0
CLK1 Pulldown
CLK_SEL Pulldown
1
IREF
D
Q
LE
PIN ASSIGNMENT
GND 1 20 Q0
CLK_EN 2 19 nQ0
CLK_SEL 3
CLK0 4
18 VDD
17 Q1
nCLK0 5 16 nQ1
Q0
nQ0
CLK1 6
Q4 7
15 Q2
14 nQ2
Q1
nQ4 8
13 VDD
nQ1 IREF 9 12 Q3
VDD 10 11 nQ3
Q2
nQ2 ICS85105I
Q3 20-Lead TSSOP
nQ3 6.5mm x 4.4mm x 0.925mm Package Body
G Package
Q4
nQ4
Top View
IDT™ / ICS™ 0.7V HCSL FANOUT BUFFER
1
ICS85105AGI REV. A JUNE 5, 2008
1 page  
ICS85105I
LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
TABLE
5.
AC
CHARACTERISTICS,
V
DD
=
3.3V±10%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX Output Frequency
CLK_SEL = 0
CLK_SEL = 1
500 MHz
250 MHz
tPD Propagation Delay; NOTE 1
CLK_SEL = 0
CLK_SEL = 1
2.0
2.0
3.2 ns
2.8 ns
tsk(o) Output Skew; NOTE 2, 4
100 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4
600 ps
tjit
VMAX
VMIN
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Absolute Maximum Output Voltage;
NOTE 5, 10
Absolute Minimum Output Voltage;
NOTE 5, 11
100MHz (12kHz - 20MHz)
-300
0.24
1150
ps
mV
mV
VRB Ringback Voltage; NOTE 6, 13
-100
100 V
tSTABLE Time before VRB is allowed; NOTE 6, 13
500 ps
V
CROSS
ΔVCROSS
Absolute Crossing Voltage; NOTE 5, 8, 9
Total Variation of VCROSS over all edges;
NOTE 5, 8, 12
Rise/Fall Edge Rate; NOTE 6, 7
Measured between
-150mV to +150mV
250
0.6
550 mV
140 mV
5.5 V/ns
odc Output Duty Cycle; NOTE 14
45 55 %
All parameters measured at IJ 250MHz unless noted otherwise.
NOTE 1: Measured from the V /2 of the input to the differential output crossing point.
DD
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output
differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Measurement taken from single-ended waveform.
NOTE 6: Measurement taken from differential waveform.
wwwN.ODTatEaS7h:eMete4aUs.cuormed from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be
monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential
zero crossing. See Parameter Measurement Information Section.
NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all
crossing points for this measurement. See Parameter Measurement Information Section.
NOTE 10: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 11: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 12: Defined as the total variation of all crossing voltage of Rising Qx and Falling nQx. This is the maximum allowed variance
in the V for any particular system. See Parameter Measurement Information Section.
CROSS
NOTE: 13. TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges
before it is allowed to droop back into the VRB ±100mV differential range. See Parameter Measurement Information Section.
NOTE 14: Input duty cycle must be 50%.
IDT™ / ICS™ 0.7V HCSL FANOUT BUFFER
5
ICS85105AGI REV. A JUNE 5, 2008
5 Page 
ICS85105I
LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
RECOMMENDED TERMINATION
Figure 4A is the recommended termination for applications
which require the receiver and driver to be on a separate PCB.
All traces should be 50Ω impedance.
FIGURE 4A. RECOMMENDED TERMINATION
Figure 4B is the recommended termination for applications
which require a point to point connection and contain the driver
and receiver on the same PCB. All traces should all be 50Ù
impedance.
www.DataSheet4U.com
FIGURE 4B. RECOMMENDED TERMINATION
IDT™ / ICS™ 0.7V HCSL FANOUT BUFFER
11
ICS85105AGI REV. A JUNE 5, 2008
11 Page | ||
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| PDF Descargar | [ Datasheet ICS85105I.PDF ] | |
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