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PDF WCMS0808U1X Data sheet ( Hoja de datos )

Número de pieza WCMS0808U1X
Descripción 32K x 8 Static RAM
Fabricantes Weida Semiconductor 
Logotipo Weida Semiconductor Logotipo



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No Preview Available ! WCMS0808U1X Hoja de datos, Descripción, Manual

S0808U1X
WCMS0808U1X
Features
• Low voltage range:
2.7V 3.6V
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The WCMS0808U1X is composed of a high-performance
CMOS static RAM organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state driv-
ers. These devices have an automatic power-down feature,
Logic Block Diagram
A10
A9
A8
A7
A6
A5
www.DataSheet4U.Ac4om
A3
A2
CE
WE
OE
INPUTBUFFER
512x512
ARRAY
COLUMN
DECODER
POWER
DOWN
32K x 8 Static RAM
reducing the power consumption by over 99% when deselect-
ed. The WCMS0808U1X is available in the 450-mil-wide
(300-mil body width) narrow SOIC and TSOP.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O0
through I/O7) is written into the memory location addressed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Pin Configurations
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7 OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A10
A11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
Narrow
SOIC
Top View
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 A4
25 A3
24 A2
23 A1
22 OE
21 A0
20 CE
19
18
I/O7
I/O6
17 I/O5
16 I/O4
15 I/O3
TSOP I
Top View
(not to scale)
21 A0
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
14 GND
13 I/O2
12 I/O1
11 I/O0
10 A14
9 A13
8 A12

1 page




WCMS0808U1X pdf
Switching Waveforms
Read Cycle No. 1[10, 11]
ADDRESS
DATA OUT
tOHA
PREVIOUS DATA VALID
tAA
tRC
WCMS0808U1X
DATA VALID
Read Cycle No. 2 [11, 12]
CE
tACE
OE
DATA OUT
VCC
SUPPLY
CURRENT
tDOE
t LZOE
HIGH IMPEDANCE
tLZCE
t PU
50%
www.DatNaoStheese: t4U.com
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
t RC
DATA VALID
t HZOE
tHZCE
HIGH
IMPEDANCE
t PD
50%
ICC
ISB
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