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PDF WCMA2016U4B Data sheet ( Hoja de datos )

Número de pieza WCMA2016U4B
Descripción 128K x 16 Static RAM
Fabricantes Weida Semiconductor 
Logotipo Weida Semiconductor Logotipo



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No Preview Available ! WCMA2016U4B Hoja de datos, Descripción, Manual

1*WCMA2016U4B
WCMA2016U4B
Features
• High Speed
— 55ns and 70ns speed availability
• Low Voltage range:
— 2.7V-3.3V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1MHz
— Typical active current: 7 mA @ f = fmax
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The WCMA2016U4B is a high-performance CMOS static
RAMs organized as 128K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active cur-
rent. This device is ideal for portable applications such as cel-
lular telephones. The devices also have an automatic pow-
er-down feature that significantly reduces power consumption
by 80% when addresses are not toggling. The device can also
128K x 16 Static RAM
be put into standby mode reducing power consumption by
more than 99% when deselected (CE HIGH or both BLE and
BHE are HIGH). The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), both Byte High En-
able and Byte Low Enable are disabled (BHE, BLE HIGH), or
during a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE ) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE ) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE ) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The WCMA2016U4B is available in a 48-ball FBGA package.
Logic Block Diagram
www.DataSheet4U.com
A 101 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
128K x 16
RAM Array
2048 x 1024
I/O0 – I/O7
I/O8 – I/O15
COLUMN DECODER
Powe r -Down
Circuit
CE
BHE
BLE
BHE
WE
CE
OE
BLE

1 page




WCMA2016U4B pdf
WCMA2016U4B
Switching Characteristics Over the Operating Range[8]
55ns
70 ns
Parameter
Description
Min Max Min Max Unit
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
t
[10]
LZBE
tHZBE
WRITE CYCLE[12]
Read Cycle Time
55 70 ns
Address to Data Valid
55 70 ns
Data Hold from Address Change
10
10
ns
CE LOW to Data Valid
55 70 ns
OE LOW to Data Valid
OE LOW to Low Z[9]
OE HIGH to High Z[9, 11]
CE LOW to Low Z[9]
CE HIGH to High Z[9, 11]
25 35 ns
5 5 ns
25 25 ns
10 10 ns
25 25 ns
CE LOW to Power-Up
0
0 ns
CE HIGH to Power-Down
55 70 ns
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z[9]
BHE / BLE HIGH to High Z[9, 11]
55 70 ns
5 5 ns
25 25 ns
tWC
Write Cycle Time
55 70 ns
tSCE
CE LOW to Write End
45
60
ns
tAW
Address Set-Up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0 ns
tSA
Address Set-Up to Write Start
0
0 ns
tPWE
WE Pulse Width
40 50 ns
tBW
BHE / BLE Pulse Width
50
60
ns
www.DattSaDSheet4U.com
Data Set-Up to Write End
25
30
ns
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High Z[9, 11]
WE HIGH to Low Z[9]
0 0 ns
20 25 ns
5 10 ns
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.) /2, input pulse levels of 0 to V CC(typ.), and output loading of
the specified IOL/IOH and 30 pF load capacitance.
9. At any given temperature and voltage condition, t HZCE is less than tLZCE, tHZBE is less than tLZBE, t HZOE is less than t LZOE, and t HZWE is less than tLZWE for
any given device.
10. If both byte enables are toggled together this value is 10ns
11. tHZOE, t HZCE, tHZBE, and t HZWE transitions are measured when the outputs enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = VIL , BHE and/or BLE = V IL. All signals must be ACTIVE to initiate a write and
any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates the write..
5

5 Page





WCMA2016U4B arduino
WCMA2016U4B
Package Diagrams
48-Ball (6.0 mm x 8.0 mm x 1.0 mm) Fine Pitch BGA, FB48A
Top View
Bottom View
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