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PDF KFG1G16Q2C Data sheet ( Hoja de datos )

Número de pieza KFG1G16Q2C
Descripción 1Gb OneNAND C-die
Fabricantes Samsung Electronics 
Logotipo Samsung Electronics Logotipo



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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
KFG1G16Q2C
1Gb OneNAND C-die
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
www.DataSheAetN4UD.cIoSmSUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
OneNAND‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be claimed as
the property of their rightful owners.
* Samsung Electronics reserves the right to change products or specification without notice.
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KFG1G16Q2C pdf
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
1.4 Product Features
Device Architecture
Design Technology:
Supply Voltage:
Host Interface:
5KB Internal BufferRAM:
SLC NAND Array:
Device Performance
Host Interface Type:
Programmable Burst Read Latency:
Multiple Sector Read/Write:
Multiple Reset Modes:
Multi Block Erase:
Low Power Dissipation:
www.DataSheet4U.com
C die
1.8V (1.7V ~ 1.95V)
16 bit
1KB BootRAM, 4KB DataRAM
(2K+64)B Page Size, (128K+4K)B Block Size
Synchronous Burst Read
- Up to 66MHz / 83MHz clock frequency
- Linear Burst 4-, 8-, 16-, 32-words with wrap around
- Continuous 1K words Sequential Burst
Synchronous Burst Block Read
- Up to 66MHz / 83MHz clock frequency
- Linear Burst 4-, 8-, 16-, 32-, 1K-words with no-wrap
- Continuous (1K words) 64 Page Sequential Burst
Synchronous Write
- Up to 66MHz / 83MHz clock frequency
- Linear Burst 4-, 8-, 16-, 32-, 1K-words with wrap around
- Continuous 1K words Sequential Burst
Asynchronous Random Read
- 76ns access time
Asynchronous Random Write
Latency 3,4(Default),5,6 and 7.
1~40MHz : Latency 3 available
1~66MHz : Latency 4,5,6 and 7 available
Over 66MHz : Latency 6,7 available.
Up to 4 sectors using Sector Count Register
Cold/Warm/Hot/NAND Flash Core Reset
up to 64 Blocks
Typical Power,
- Standby current : 10uA
- Synchronous Burst Read current(66/83MHz) : 15/20mA
- Synchronous Burst Write current(66/83MHz) : 15/20mA
- Load current : 30mA
- Program current : 25mA
- Erase current : 20mA
- Multi Block Erase current : 20mA
Reliability
- Data retention 10year after 10K Program/Erase Cycles
- Data retention 1 year after 100K Program/Erase Cycles
System Hardware
Voltage detector generating internal reset signal from Vcc
Hardware reset input (RP)
Data Protection Modes
User-controlled One Time Programmable(OTP) area
Internal 2bit EDC / 1bit ECC
Internal Bootloader supports Booting Solution in system
Handshaking Feature
Detailed chip information
- Write Protection for BootRAM
- Write Protection for NAND Flash Array
- Write Protection during power-up
- Write Protection during power-down
- 1st block OTP
- INT pin indicates Ready / Busy
- Polling the interrupt register status bit
- by ID register
Packaging
1Gb products
63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA
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KFG1G16Q2C arduino
OneNAND1Gb(KFG1G16Q2C-xEBx)
2.5 Block Diagram
DQ15~DQ0
A15~A0
CLK
CE
OE
WE
RP
AVD
INT
RDY
BufferRAM
BootRAM
DataRAM0
DataRAM1
Bootloader
StateMachine
Internal Registers
(Address/Command/Configuration
/Status Registers)
Error
Correction
Logic
FLASH MEMORY
1st Block OTP
(Block 0)
NAND Flash
Array
OTP
(One Block)
2.6 Memory Array Organization
The OneNAND architecture integrates several memory areas on a single chip.
2.6.1 Internal (NAND Array) Memory Organization
www.DaTmtahaSeinhoeaner-etc4ahUiap.ncidonmtaersnpaal rme eamreoar.y is a single-level-cell (SLC) NAND array used for data storage and code. The internal memory is divided into a
Main Area
The main area is the primary memory array. This main area is divided into Blocks of 64 Pages. Within a Block, each Page is 2KB and is com-
prised of 4 Sectors. Within a Page, each Sector is 512B and is comprised of 256 Words.
Spare Area
The spare area is used for invalid block information and ECC storage. Spare area internal memory is associated with corresponding main
area memory. Within a Block, each Page has four 16B Sectors of spare area. Each spare area Sector is 8 words.
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