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PDF UPD72852A Data sheet ( Hoja de datos )
| Número de pieza | UPD72852A | |
| Descripción | IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72852A
IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI
The µPD72852A is a two-port physical layer LSI that complies with the IEEE1394a-2000 specifications.
FEATURES
• The two-port physical layer LSI complies with IEEE1394a-2000
• Fully interoperable with IEEE1394 std 1394 Link (FireWireTM, i.LINKTM)
• Meets IntelTM Mobile Power Guideline 2000
• Full IEEE1394a-2000 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset, multi-speed
concatenation, arbitration acceleration, fly-by concatenation
• Suspend Debounce timer for ESD
• “BIAS Detected” signal output
• Double speed signal filter for BIAS Ringing
• Small package: 64-pin plastic LQFP
• Super low power : 68 mA (Operating mode)
: 115 µA (Suspend mode)
• Data rate: 400/200/100 Mbps
• Supports PHY pinging and remote PHY access packets
• 3.3 V single power supply (if power not supplied via node: 3.0 V single power supply)
• 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency
• 64-bit flexible register incorporated in PHY register
www.Da•taSEhleeectt4rUic.aclolymisolated Link interface
• Supports LPS/Link-on as part of PHY/Link interface
• External filter capacitors for PLL not required
• Extended Resume signaling for compatibility with legacy DV devices
• System power management by signaling of node power class information
• Cable power monitor (CPS) is equipped
ORDERING INFORMATION
Part number
µPD72852AGB-8EU
Package
64-pin plastic LQFP (10 × 10)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No.
Date Published
Printed in Japan
S16725EJ2V0DS00 (2nd edition)
March 2004 NS CP (K)
The mark shows major revised points.
2003
1 page  
µPD72852A
CONTENTS
1. PIN FUNCTIONS..................................................................................................................................... 7
1.1 Cable Interface Pins ........................................................................................................................ 7
1.2 Link Interface Pins .......................................................................................................................... 7
1.3 Control Pins ..................................................................................................................................... 8
1.4 IC ....................................................................................................................................................... 8
1.5 Power Supply Pins .......................................................................................................................... 8
1.6 Other Pins ........................................................................................................................................ 9
2. PHY REGISTERS .................................................................................................................................. 10
2.1 Complete Structure for PHY Registers ....................................................................................... 10
2.2 Port Status Page (Page 000) ........................................................................................................ 13
2.3 Vendor ID Page (Page 001)........................................................................................................... 14
2.4 Vendor Dependent Page (Page 111 : Port_select 0000)............................................................ 14
2.5 Vendor Dependent Page (Page 111 : Port_select 0001)............................................................ 15
3. INTERNAL FUNCTION.......................................................................................................................... 16
3.1 Link Interface ................................................................................................................................. 16
3.1.1 Connection Method ............................................................................................................................... 16
3.1.2 LPS (Link Power Status) ....................................................................................................................... 16
3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins..................................................................................................... 16
3.1.4 SCLK..................................................................................................................................................... 16
3.1.5 LKON .................................................................................................................................................... 17
3.1.6 DIRECT................................................................................................................................................. 17
3.1.7 Isolation Barrier ..................................................................................................................................... 17
3.2 Cable Interface............................................................................................................................... 19
3.2.1 Connections .......................................................................................................................................... 19
3.2.2 Cable Interface Circuit........................................................................................................................... 20
3.2.3 Unused Ports ........................................................................................................................................ 20
www.DataSheet4U.co3m.2.4 CPS....................................................................................................................................................... 20
3.3 Suspend/Resume .......................................................................................................................... 20
3.3.1 Suspend/Resume On Mode (SUS/RES = “H”)...................................................................................... 20
3.3.2 Suspend/Resume Off Mode (SUS/RES = “L”) ...................................................................................... 20
3.4 PLL and Crystal Oscillation Circuit ............................................................................................. 21
3.4.1 Crystal Oscillation Circuit ...................................................................................................................... 21
3.4.2 PLL........................................................................................................................................................ 21
3.5 CMC ................................................................................................................................................ 21
3.6 PC0-PC2 ......................................................................................................................................... 21
3.7 RESETB .......................................................................................................................................... 21
3.8 RI1 ................................................................................................................................................... 21
4. PHY/LINK INTERFACE ......................................................................................................................... 22
4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface............................................ 22
4.2 Link-on Indication ......................................................................................................................... 23
4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7) ...................................................... 24
4.3.1 CTL0, CTL1 .......................................................................................................................................... 24
4.3.2 LREQ .................................................................................................................................................... 24
Data Sheet S16725EJ2V0DS
5
5 Page 
µPD72852A
Field
Total_ports
Max_speed
Delay
Link_active
Contender
Jitter
Pwr_class
Watchdog
www.DataSheet4U.com
ISBR
Loop
Pwr_fail
Table 2-1. Bit Field Description (2/3)
Size R/W Reset value
Description
4R
0010
Supported port number.
0010: 2 ports
3R
See Indicate the maximum speed that this node supports.
Description Set variable by SPD pin (61 pin).
When SPD = “0” then 001: 98.304 and 196.608 Mbps.
When SPD = “1” then 010: 98.304, 196.608 and 393.216 Mbps.
4R
0000
Indicate worst case repeating delay time. 144 + (Delay × 20) = 144 nsec
1 R/W
1 Link active.
1: Enable
0: Disable
The logical AND status of this bit and LPS pin.
State will be referred to “L bit” of Self-ID Packet#0.
1 R/W See Contender.
Description “1” indicate this node support bus manager function. This bit will be referred
to “C bit” of Self-ID Packet#0.
The reset data is depending on CMC pin setting.
CMC pin condition
1: Pull up (Contender)
0: Pull down (Non Contender)
3R
010 The difference of repeating time (Max.-Min.). (2+1) × 20 = 60 nsec
3 R/W See Power class.
Description Please refer to IEEE1394a-2000 [4.3.4.1].
This bit will be referred to Pwr field of Self-ID Packet#0.
The reset data will be determined by PC0-PC2 Pin status.
1 R/W 0 Watchdog Enable.
This bit serves two purposes.
When set to 1, if any one port does resume, the Port_event bit becomes 1.
This function has no effect when SUS/RES (19 pin) = “0”.
To determine whether or not an interrupt condition shall be indicated to the
Link. On condition of LPS = 0 and Watchdog = 0, LKON as interrupt of Loop,
Pwr_fail, Timeout is not output. This function has effect both when SUS/RES
(19 pin) = “1” or “0”.
1 R/W
0 Initiate short (arbitrated) bus reset.
Setting to 1 acquires the bus and begins short bus reset.
Short bus reset signal output : 1.3 µsec
Returns to 0 at the beginning of the bus reset.
1 R/W
0 Loop detection output.
1: Detection
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
1 R/W
1 Power cable disconnect detect.
It becomes 1 when there is a change from 1 to 0 in the CPS bit.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Data Sheet S16725EJ2V0DS
11
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