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PDF LC66508B Data sheet ( Hoja de datos )

Número de pieza LC66508B
Descripción Four-Bit Single-Chip Microcontrollers with 4/ 6/ 8/ 12/ and 16 KB of On-Chip ROM
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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No Preview Available ! LC66508B Hoja de datos, Descripción, Manual

Ordering number : EN5996
CMOS IC
LC662104A, 662106A, 662108A
Four-Bit Single-Chip Microcontrollers
with 4, 6, and 8 KB of On-Chip ROM
Overview
The LC662104A, LC662106A, and LC662108A are 4-bit
CMOS microcontrollers that integrate on a single chip all
the functions required in a special-purpose telephone
controller, including ROM, RAM, I/O ports, a serial
interface, a DTMF generator, timers, and interrupt
functions. These microcontrollers are available in a 30-pin
package.
Features and Functions
• On-chip ROM capacities of 4, 6, and 8 kilobytes, and an
on-chip RAM capacity of 384 × 4 bits.
• Fully supports the LC66000 Series common instruction
set (128 instructions). (The special-purpose instructions
for TM1 and SI/01 are disabled.)
• I/O ports: 24 pins
• DTMF generator
This microcontroller incorporates a circuit that can
generate two sine wave outputs, DTMF output.
• 8-bit serial interface: one circuit
• Instruction cycle time: 0.95 to 10 µs (at 3.0 to 5.5 V)
• Powerful timer functions and prescalers
— Time limit timer, event counter, pulse width
measurement, and square wave output using a 12-bit
timer.
— Time base function using a 12-bit prescaler.
• Powerful interrupt system with 6 interrupt factors and 6
interrupt vector locations.
— External interrupts: 3 factors/3 vector locations
— Internal interrupts: 3 factors/3 vector locations
• Flexible I/O functions
Selectable options include 20-mA drive outputs, pull-up
and open drain circuits.
• Optional runaway detection function (watchdog timer)
• 8-bit I/O functions
• Power saving functions using halt and hold modes.
• Packages: DIP30SD, MFP30S
• Evaluation ICs: LC665099 (evaluation chip) + EVA86K
- ECB662500
LC66E2108(on-chip EPROM microcontroller)
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
101698RM (OT) No. 5966-1/13

1 page




LC66508B pdf
LC662104A, 662106A, 662108A
Pin Function Overview
Pin I/O
Overview
Output driver type
Options
State after a
reset
P00
P01
P02
P03
I/O ports P00 to P03
• Input or output in 4-bit or 1-bit units
I/O • P00 to P03 support the halt mode
control function (This function can be
specified in bit units.)
• Pch: Pull-up MOS type
• Pull-up MOS or Nch
• Nch: Intermediate sink current OD output
type • Output level on reset
High or low (option)
P10
P11
P12
I/O
I/O ports P10 to P13
Input or output in 4-bit or 1-bit units
P13
• Pch: Pull-up MOS type
• Pull-up MOS or Nch
• Nch: Intermediate sink current OD output
type • Output level on reset
High or low (option)
P20/SI0
P21/SO0
P22/SCK0
P23/INT0
I/O ports P20 to P23
• Input or output in 4-bit or 1-bit units
• P20 is also used as the serial input SI0
I/O
pin.
• P21 is also used as the serial output
SO0 pin.
• P22 is also used as the serial clock
SCK0 pin.
• P23 is also used as the INT0 interrupt
• Pch: CMOS type
• Nch: Intermediate sink current
type
• Nch: +15V handling when OD
option selected
CMOS or Nch OD
output
request pin, and also as the timer 0
event counting and pulse width
measurement input.
H
I/O ports P30 to P32
P30/INT1
P31/POUT0
P32
I/O
• Input or output in 3-bit or 1-bit units
• P30 is also used as the INT1 interrupt
request.
• P31 is also used for the square wave
output from timer 0.
• P31 and P32 also support 3-state
• Pch: CMOS type
• Nch: Intermediate sink current
type
• Nch: +15V handling when OD
option selected
CMOS or Nch OD
output
outputs.
H
P33/HOLD
Hold mode control input
• Hold mode is set up by the HOLD
instruction when HOLD is low.
• In hold mode, the CPU is restarted by
setting HOLD to the high level.
I
• This pin can be used as input port P33
along with P30 to P32.
• When the P33/HOLD pin is at the low
level, the CPU will not be reset by a
low level on the RES pin. Therefore,
applications must not set P33/HOLD
low when power is first applied.
I/O ports P40 to P43
P40
P41
P42
• Input or output in 4-bit or 1-bit units
• Pch: Pull-up MOS type
• Input or output in 8-bit units when used • Nch: Intermediate sink current • Pull-up MOS or Nch
I/O in conjunction with P50 to P53.
type
OD output
High or low (option)
P43
• Can be used for output of 8-bit ROM
data when used in conjunction with
• Nch: +15V handkling when
OD option selected
• Output level on reset
P50 to P53.
Continued on next page.
No. 5996-5/13

5 Page





LC66508B arduino
LC662104A, 662106A, 662108A
Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V unless otherwise specified.
Parameter
Input high-level current
Input low-level current
Output high-level voltage
Value of the output pull-up resistor
Output low-level voltage
Output off leakage current
[Schmitt characteristics]
Hysteresis voltage
High-level threshold voltage
Low-level threshold voltage
[Ceramic oscillator]
Oscillator frequency
Oscillator stabilization time
[Serial clock]
Cycle time
Input
Output
Low-level and high-level Input
pulse widths
Output
Rise an fall times
Output
[Serial input]
Symbol
IIH1
IIH2
IIL1
VOH1
RPO
VOL1
VOL2
IOFF1
IOFF2
VHYS
VtH
VtL
fCF
fCFS
tCKCY
tCKL
tCKH
tCKR, tCKF
Conditions
P2, P3 (except for the P33/HOLD pin), P4,
P51, and P53: VIN = 13.5 V, with the output
Nch transistor off
P0, P1, P50, P52, OSC1, RES, and P33/HOLD:
VIN = VDD, with the output Nch transistor off
P0, P1, P2, P3, P4, and P5:
VIN = VSS, with the output Nch transistor off
P2, P3 (except for the IOH = –1 mA
P33/HOLD pin)
IOH = –0.1 mA
P0, P1, P4, P5
P0, P1, P2, P3, P4, and P5
(except for the P33/HOLD pin): IOL = 1.6 mA
P0, P1, P2, P3, P4, and P5
(except for the P33/HOLD pin): IOL = 8 mA
P2, P3, P4, P51, and P53: VIN = 13.5 V
Does not apply to P2, P3, P4, P51, and P53:
VIN = VDD
P2, P3, P4, P5, and RES
OSC1, OSC2: See Figure 2. 4 MHz
See Figure 3. 4 MHz
SCK0: With the timing of Figure 4 and the test
load of Figure 5.
min
–1.0
VDD – 1.0
VDD – 0.5
30
0.5 VDD
0.2 VDD
0.9
2.0
0.4
1.0
Ratings
typ
100
0.1 VDD
4.0
max
5.0
1.0
150
0.4
1.5
5.0
1.0
0.8 VDD
0.5 VDD
10.0
0.1
Unit Note
µA 1
µA 1
µA 2
V3
k
V5
V
µA 6
µA 6
V
V
MHz
ms
µs
Tcyc
µs
Tcyc
µs
Data setup time
Data hold time
[Serial output]
Output delay time
[Pulse conditions]
INT0 high and low-level
High and low-level pulse widths
for interrupt inputs other than INT0
RES high and low-level
pulse widths
tICK
tCKI
tCKO
tIOH, tIOL
tIIH, tIIL
tRSH, tRSL
SI0: With the timing of Figure 4.
Stipulated with respect to the rising edge () of
SCK0.
SO0: With the timing of Figure 4 and the test
load of Figure 5. Stipulated with respect to the
falling edge () of SCK0.
INT0: Figure 6, conditions under which the INT0
interrupt can be accepted, conditions under
which the timer 0 event counter or pulse width
measurement input can be accepted
INT1, INT2: Figure 6, conditions under which
the corresponding interrupt can be accepted
RES: Figure 6, conditions under which reset
can be applied.
0.3
0.3
2
2
3
µs
µs
0.3 µs
Tcyc
Tcyc
Tcyc
Operating current drain
IDD OP
VDD: 4-MHz ceramic oscillator
VDD: 4-MHz external clock
4.5 8.0 mA
8
4.5 8.0 mA
Halt mode current drain
IDDHALT
VDD: 4-MHz ceramic oscillator
VDD: 4-MHz external clock
2.5 5.5 mA
2.5 5.5 mA
Hold mode current drain
IDDHOLD VDD: VDD = 1.8 to 5.5 V
0.01
10 µA
Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the
CMOS output specifications are selected.
2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is
stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected.
3. With the output Nch transistor off for CMOS output specification pins.
4. With the output Nch transistor off for pull-up output specification pins.
6. With the output Pch transistor off for open-drain output specification pins.
7. Reset state
No. 5996-11/13

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