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PDF 93AA56C Data sheet ( Hoja de datos )

Número de pieza 93AA56C
Descripción (93AAxxx) 1K-16K Microwire Compatible Serial EEPROMs
Fabricantes Microchip Technology 
Logotipo Microchip Technology Logotipo



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No Preview Available ! 93AA56C Hoja de datos, Descripción, Manual

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
1K-16K Microwire Compatible Serial EEPROMs
Features:
• Densities from 1 Kbits through 16 Kbits
• Low-power CMOS technology
• Available with or without ORG function:
With ORG function:
- ORG pin at Logic Low: 8-bit word
- ORG pin at Logic High: 16-bit word
Without ORG function:
- ‘A’ version: 8-bit word
- ‘B’ version: 16-bit word
• Program Enable pin:
- Write-protect for entire array
(93XX76C and 93XX86C only)
• Self-timed Erase/Write cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power-on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device Status signal (Ready/Busy)
• Sequential Read function
• 1,000,000 E/W cycles
• Data retention > 200 years
• Pb-free and RoHS compliant
• Temperature ranges supported:
www.DataSheet4U.com
- Industrial (I)
-40°C to +85°C
- Automotive (E)
-40°C to +125°C
Pin Function Table
Name
Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
VSS Ground
PE Program Enable
ORG Memory Configuration
VCC
Note:
Power Supply
ORG and PE functionality not available in
all products. See Table 1-1, Device
Selection Table.
Description:
Microchip Technology Inc. supports the 3-wire
Microwire bus with low-voltage serial Electrically
Erasable PROMs (EEPROM) that range in density
from 1 Kbits up to 16 Kbits. Each density is available
with and without the ORG functionality, and selected
by the part number ordered. Advanced CMOS technol-
ogy makes these devices ideal for low-power, nonvol-
atile memory applications. The entire series of
Microwire devices are available in the standard 8-lead
PDIP and SOIC packages, as well as the more
advanced packaging such as the 8-lead MSOP, 8-lead
TSSOP, 6-lead SOT-23, and 8-lead DFN (2x3). All
packages are Pb-free.
Pin Diagrams (not to scale)
PDIP/SOIC
(P, SN)
CS 1
CLK 2
DI 3
DO 4
8
7
6
5
ROTATED SOIC
(ex: 93LC46BX)
VCC
NC
(2,3)
PE VCC
(1,3)
ORG CS
1
2
3
(1,3)
8 ORG
7 VSS
6 DO
VSS CLK 4
5 DI
DFN (MC)
CS 1
CLK 2
DI 3
DO 4
8 VCC
7 PE(2,3)
6 ORG(1,3)
5 VSS
TSSOP/MSOP
(ST, MS)
CS
CLK
DI
DO
1
2
3
4
8 VCC
DO
7 PE(2,3)
6 ORG(1,3) VSS
5 VSS
DI
SOT-23
(OT)
16
25
34
VCC
CS
CLK
Note 1: ORG pin: Only on 93XX46C/56C/66C/76C/86C.
2: PE pin: Only on 93XX76C/86C.
3: ORG/PE: No internal connections on 93XXA/B.
© 2007 Microchip Technology Inc.
DS21929D-page 1

1 page




93AA56C pdf
93XX46X/56X/66X/76X/86X
TABLE 2-2: AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
VCC = 1.8V to 5.5V
Industrial (I): TA = -40°C to +85°C
Automotive (E): TA = -40°C to +125°C
Param.
No.
Symbol
Parameter
Min.
Max. Units
Conditions
A1
FCLK
Clock frequency
— 3 MHz 4.5V VCC < 5.5V
2 MHz 2.5V VCC < 4.5V
1 MHz 1.8V VCC < 2.5V
A2
TCKH
Clock high time
200 — ns 4.5V VCC < 5.5V
250 ns 2.5V VCC < 4.5V
450 ns 1.8V VCC < 2.5V
A3
TCKL
Clock low time
100 — ns 4.5V VCC < 5.5V
200 ns 2.5V VCC < 4.5V
450 ns 1.8V VCC < 2.5V
A4
TCSS
Chip Select setup time
50 — ns 4.5V VCC < 5.5V
100 ns 2.5V VCC < 4.5V
250 ns 1.8V VCC < 2.5V
A5 TCSH Chip Select hold time
0 — ns 1.8V VCC < 5.5V
A6
TCSL
Chip Select low time
250 — ns 1.8V VCC < 5.5V
A7 TDIS Data input setup time
50 — ns 4.5V VCC < 5.5V
100 ns 2.5V VCC < 4.5V
250 ns 1.8V VCC < 2.5V
A8 TDIH Data input hold time
50 — ns 4.5V VCC < 5.5V
100 ns 2.5V VCC < 4.5V
250 ns 1.8V VCC < 2.5V
A9 TPD Data output delay time
— 100 ns 4.5V VCC < 5.5V, CL = 100 pF
(93C76X/86X)
www.DataSheeAt41U0.com TCZ
Data output disable time
— 200 ns 4.5V VCC < 5.5V, CL = 100 pF
250 ns 2.5V VCC < 4.5V, CL = 100 pF
400 ns 1.8V VCC < 2.5V, CL = 100 pF
— 100 ns 4.5V VCC < 5.5V, (Note 1)
200 ns 1.8V VCC < 4.5V, (Note 1)
A11 TSV
Status valid time
— 200 ns 4.5V VCC < 5.5V, CL = 100 pF
300 ns 2.5V VCC < 4.5V, CL = 100 pF
500 ns 1.8V VCC < 2.5V, CL = 100 pF
A12 TWC
Program cycle time
— 5 ms Erase/Write mode
93XX76X/86X
(AA and LC versions)
— 6 ms 93XX46X/56X/66X
(AA and LC versions)
A13 TWC
— 2 ms 93C46X/56X/66X/76X/86X
A14 TEC
Program cycle time
— 6 ms ERAL mode, 4.5V VCC 5.5V
A15 TWL
— 15 ms WRAL mode, 4.5V VCC 5.5V
A16 —
Endurance
1M — cycles 25°C, VCC = 5.0V, (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which may be downloaded from Microchip’s web
site at www.microchip.com.
© 2007 Microchip Technology Inc.
DS21929D-page 5

5 Page





93AA56C arduino
93XX46X/56X/66X/76X/86X
3.4 ERASE
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. CS is brought
low following the loading of the last address bit. This
falling edge of the CS pin initiates the self-timed
programming cycle, except on ‘93CXX’ devices where
the rising edge of CLK before the last address bit
initiates the write cycle.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/Busy status from DO.
FIGURE 3-1:
CS
ERASE TIMING FOR 93AAXX AND 93LCXX DEVICES
TCSL
Check Status
CLK
DI 1 1 1 AN AN-1 AN-2 ••• A0
DO High-Z
TSV
BUSY
TWC
TCZ
Ready
High-Z
FIGURE 3-2:
CS
www.DataSheet4CUL.Kcom
ERASE TIMING FOR 93CXX DEVICES
TCSL
Check Status
DI 1 1 1 AN AN-1 AN-2 ••• A0
DO High-Z
TSV
Busy
TWC
TCZ
Ready
High-Z
© 2007 Microchip Technology Inc.
DS21929D-page 11

11 Page







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