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PDF AD5542A Data sheet ( Hoja de datos )

Número de pieza AD5542A
Descripción (AD5512A - AD5542A) 16-/12-Bit NanoDAC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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2.7 V to 5.5 V, Serial-Input, Voltage-Output,
16-/12-Bit nanoDACs in LFCSP
Preliminary Technical Data
AD5541A/AD5542A/AD5512A
FEATURES
Low power, 1 LSB INL nanoDACs
AD5541A: 16 bits
AD5542A: 16 bits
AD5512A: 12 bits
2.7 V to 5.5 V single-supply operation
Low glitch: 0.5 nV-s
Unbuffered voltage output capable of driving 60 kΩ loads
directly
VLOGIC pin provides 1.8 V digital interface capability
Hardware CLR and LDAC functions
50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface
standards
Power-on reset clears DAC output to zeroscale and midscale
Schmitt trigger inputs
Available in 3 mm × 3 mm 16-LFCSP, 10-LFCSP, and 8-LFCSP
Also available in10-MSOP and 16-TSSOP
APPLICATIONS
Automatic test equipment
Precision Source-measure Instruments
Data Acquisition Systems
Medical Instrumentation
Aerospace Instrumentation
Communications Infrastructure equipment
Industrial Control
GENERAL DESCRIPTION
The AD5541A/AD5542A/AD5512A1 are single, 16-/16-/12-bit,
www.DasetariSahleinept4uUt,.cuonmbuffered voltage output digital-to-analog conver-
ters (DACs) that operate from a single 2.7 V to 5.5 V supply.
The AD5541A/AD5542A/AD5512A utilize a versatile 3-wire
interface that is compatible with a 50 MHz SPI, QSPI™,
MICROWIRE™, and DSP interface standards.
These DACs provide 16-/12-bit performance without any adjust-
ments. The DAC output is unbuffered, which reduces power
consumption and offset errors contributed to by an output buffer.
The AD5542A/AD5512A can be operated in bipolar mode, which
generates a ±VREF output swing. The AD5542A/AD5512A also
includes Kelvin sense connections for the reference and analog
ground pins to reduce layout sensitivity.
The AD5541A is available in 10-lead 3 mm × 3 mm LFCSP and
10-lead MSSOP. The AD5541A-1 is available in 8-lead 3 mm ×
3 mm LFCSP. The AD5542A/AD5512A are available in 16-lead
3 mm × 3 mm LFCSP and the AD5542A is also available in
16-lead TSSOP. The AD5542A-1 is available in 10-lead LFCSP.
The AD5541A and AD5542A are specified over a temperature
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
range of −40°C to 105°C.
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. AD5541A
Figure 2. AD5541A-1
Figure 3. AD5542A
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.

1 page




AD5542A pdf
Preliminary Technical Data
AD5541A/AD5542A/AD5512AA
Parameter
POWER REQUIREMENTS
VDD
IDD
VLOGIC
ILOGIC
Power Dissipation
Min Typ
2.7
200
1.8
200
1.5
Max
5.5
TBD
5.5
TBD
TBD
Unit Test Condition
V
µA
V
µA
mW
1 Reference input resistance is code-dependent, minimum at 0x8555.
2 Guaranteed by design, not subject to production test.
TIMING CHARACTERISTICS
VLOGIC = 1.8 V to 5.5 V V, VDD = 5V, VREF = 2.5 V, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V; −40°C < TA < +105°C,
unless otherwise noted.
Table 2.
Parameter1, 2
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t9
t10
t11
t12
t13
Limit
50
20
10
10
5
7
15
10
7
5
5
15
15
15
15
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time (VINH = 90% of VDD, VINL = 10% of VDD)
Data hold time (VINH = 3V, VINL = 0 V)
LDAC pulsewidth
CS high to LDAC low setup
CS high time between active periods
CLR pulsewidth
www.Da1 GtauSarhaenetet4edUb.cyodmesign and characterization. Not production tested
2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
Figure 5. Timing Diagram
Rev. PrA | Page 5 of 24

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AD5542A arduino
Preliminary Technical Data
AD5541A/AD5542A/AD5512AA
Figure 26. Digital Feedthrough
Figure 28. Large Signal Settling Time
Figure 27. Digital-to-Analog Glitch Impulse
www.DataSheet4U.com
Figure 29. Small Signal Settling Time
Rev. PrA | Page 11 of 24

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