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(AD5512A - AD5542A) 16-/12-Bit NanoDAC - AD5541A - Analog Devices

Número de pieza AD5541A
Descripción (AD5512A - AD5542A) 16-/12-Bit NanoDAC
Fabricantes Analog Devices 
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AD5541A datasheet
AD5541A pdf, arduino
Preliminary Technical Data
AD5541A/AD5542A/AD5512AA
Parameter
POWER REQUIREMENTS
VDD
IDD
VLOGIC
ILOGIC
Power Dissipation
Min Typ
2.7
200
1.8
200
1.5
Max
5.5
TBD
5.5
TBD
TBD
Unit Test Condition
V
µA
V
µA
mW
1 Reference input resistance is code-dependent, minimum at 0x8555.
2 Guaranteed by design, not subject to production test.
TIMING CHARACTERISTICS
VLOGIC = 1.8 V to 5.5 V V, VDD = 5V, VREF = 2.5 V, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V; −40°C < TA < +105°C,
unless otherwise noted.
Table 2.
Parameter1, 2
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t9
t10
t11
t12
t13
Limit
50
20
10
10
5
7
15
10
7
5
5
15
15
15
15
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time (VINH = 90% of VDD, VINL = 10% of VDD)
Data hold time (VINH = 3V, VINL = 0 V)
LDAC pulsewidth
CS high to LDAC low setup
CS high time between active periods
CLR pulsewidth
www.Da1 GtauSarhaenetet4edUb.cyodmesign and characterization. Not production tested
2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
Figure 5. Timing Diagram
Rev. PrA | Page 5 of 24





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